From ec3143f01471840134064e8b20c20a8e53a33fe5 Mon Sep 17 00:00:00 2001
From: David Harris <David_Harris@hmc.edu>
Date: Fri, 29 Nov 2024 12:03:14 -0800
Subject: [PATCH 1/3] Updated warning in ramxdetector

---
 testbench/common/ramxdetector.sv | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/testbench/common/ramxdetector.sv b/testbench/common/ramxdetector.sv
index c600cff8c..fac34fb43 100644
--- a/testbench/common/ramxdetector.sv
+++ b/testbench/common/ramxdetector.sv
@@ -39,7 +39,7 @@ module ramxdetector #(parameter XLEN, LLEN) (
     /* verilator lint_off WIDTHXZEXPAND */
     if (MemReadM & ~LSULoadAccessFaultM & (ReadDataM === 'bx)) begin
       /* verilator lint_on WIDTHXZEXPAND */
-      $display("WARNING: Attempting to read from unitialized RAM.  Processor may go haywire if it uses x value. But this is normal in WALLY-mmu tests.");
+      $display("WARNING: Attempting to read from unitialized RAM.  Processor may go haywire if it uses x value. But this is normal in WALLY-mmu and ExceptionInstr tests.");
       $display("  PCM = %x InstrM = %x (%s), IEUAdrM = %x", PCM, InstrM, InstrMName, IEUAdrM);
       //$stop;
     end

From 9d3e82d3ec17bfc0c61d4658759dca821531082e Mon Sep 17 00:00:00 2001
From: David Harris <David_Harris@hmc.edu>
Date: Fri, 29 Nov 2024 12:05:00 -0800
Subject: [PATCH 2/3] Updated imperas.ic files so rv32 follows rv64

---
 config/rv32gc/imperas.ic | 16 +++++++++++-----
 config/rv64gc/imperas.ic |  4 +---
 2 files changed, 12 insertions(+), 8 deletions(-)

diff --git a/config/rv32gc/imperas.ic b/config/rv32gc/imperas.ic
index 2ba3c1280..0c3f2e2ea 100644
--- a/config/rv32gc/imperas.ic
+++ b/config/rv32gc/imperas.ic
@@ -9,7 +9,7 @@
 #--showcommands
 
 # Core settings
---variant RV32GC # for RV32GC
+--variant RV32GCK # for RV32GC
 --override cpu/priv_version=1.12 
 --override cpu/user_version=20191213
 # arch
@@ -59,7 +59,7 @@
 #--override cpu/instret_undefined=T
 #--override cpu/hpmcounter_undefined=T
 
-## context registers not implemented
+# context registers not implemented
 #--override cpu/scontext_undefined=True
 #--override cpu/mcontext_undefined=True
 
@@ -69,9 +69,14 @@
 #--override cpu/Zicfilp=F
 --override cpu/trigger_num=0 # disable CSRs 7a0-7a8
 
---override no_pseudo_inst=T # For code coverage, don't produce pseudoinstructions
+# For code coverage, don't produce pseudoinstructions
+--override no_pseudo_inst=T 
 
---override show_c_prefix=T  # Show "c." with compressed instructions
+# Show "c." with compressed instructions 
+--override show_c_prefix=T
+
+# nonratified mnoise register not implemented
+--override cpu/mnoise_undefined=T
 
 # mcause and scause only have 4 lsbs of code and 1 msb of interrupt flag
 #--override cpu/ecode_mask=0x8000000F  # for RV32
@@ -80,7 +85,8 @@
 # Debug mode not yet supported
 --override cpu/debug_mode=none
 
-
+# Zkr entropy source and seed register not supported.
+--override cpu/Zkr=F
 
 --override cpu/reset_address=0x80000000
 
diff --git a/config/rv64gc/imperas.ic b/config/rv64gc/imperas.ic
index 9ba14f2f0..19a7515a5 100644
--- a/config/rv64gc/imperas.ic
+++ b/config/rv64gc/imperas.ic
@@ -73,7 +73,7 @@
 # Show "c." with compressed instructions 
 --override show_c_prefix=T
 
-# nonratified mnosie register not implemented
+# nonratified mnoise register not implemented
 --override cpu/mnoise_undefined=T
 
 # mcause and scause only have 4 lsbs of code and 1 msb of interrupt flag
@@ -86,8 +86,6 @@
 # Zkr entropy source and seed register not supported.
 --override cpu/Zkr=F
 
-
-
 --override cpu/reset_address=0x80000000
 
 --override cpu/unaligned=T  # Zicclsm (should be true)

From 11272984bd42afdb8796e92063f06628d568db15 Mon Sep 17 00:00:00 2001
From: David Harris <David_Harris@hmc.edu>
Date: Fri, 29 Nov 2024 14:49:48 -0800
Subject: [PATCH 3/3] Added ExceptionsZc illegal instruction coverage

---
 config/rv32gc/coverage.svh | 1 +
 config/rv64gc/coverage.svh | 1 +
 2 files changed, 2 insertions(+)

diff --git a/config/rv32gc/coverage.svh b/config/rv32gc/coverage.svh
index 115dbd5f1..90593e0f5 100644
--- a/config/rv32gc/coverage.svh
+++ b/config/rv32gc/coverage.svh
@@ -45,3 +45,4 @@
 `include "EndianM_coverage.svh"
 `include "EndianS_coverage.svh"
 `include "ExceptionsM_coverage.svh"
+`include "ExceptionsZc_coverage.svh"
diff --git a/config/rv64gc/coverage.svh b/config/rv64gc/coverage.svh
index e7c574020..6aba1ac9a 100644
--- a/config/rv64gc/coverage.svh
+++ b/config/rv64gc/coverage.svh
@@ -44,6 +44,7 @@
 `include "EndianM_coverage.svh"
 `include "EndianS_coverage.svh"
 `include "ExceptionsM_coverage.svh"
+`include "ExceptionsZc_coverage.svh"
 // `include "RV64VM_PMP_coverage.svh"
 // `include "RV64CBO_VM_coverage.svh"
 // `include "RV64CBO_PMP_coverage.svh"