From 84dac82defc8f8d837f115b5bd009a43bce29ca7 Mon Sep 17 00:00:00 2001 From: David Harris Date: Mon, 22 May 2023 09:51:46 -0700 Subject: [PATCH 1/6] Initial testbench cleanup for Verilator --- testbench/testbench.sv | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/testbench/testbench.sv b/testbench/testbench.sv index 9021b6448..0c8245948 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -320,10 +320,10 @@ module testbench; $display("Embench Benchmark: %s is done.", tests[test]); if (riscofTest) outputfile = {pathname, tests[test], "/ref/ref.sim.output"}; else outputfile = {pathname, tests[test], ".sim.output"}; - outputFilePointer = $fopen(outputfile); + outputFilePointer = $fopen(outputfile, "w"); i = 0; while ($unsigned(i) < $unsigned(5'd5)) begin - $fdisplayh(outputFilePointer, DCacheFlushFSM.ShadowRAM[testadr+i]); + $fdisplay("%x %s", outputFilePointer, DCacheFlushFSM.ShadowRAM[testadr+i]); i = i + 1; end $fclose(outputFilePointer); @@ -574,7 +574,7 @@ module testbench; assign InvalEdge = dut.core.ifu.InvalidateICacheM & ~InvalDelayed; initial begin - LogFile = $psprintf("ICache.log"); + LogFile = "ICache.log"; file = $fopen(LogFile, "w"); $fwrite(file, "BEGIN %s\n", memfilename); end @@ -617,7 +617,7 @@ module testbench; (AccessTypeString != "NULL"); initial begin - LogFile = $psprintf("DCache.log"); + LogFile = "DCache.log"; file = $fopen(LogFile, "w"); $fwrite(file, "BEGIN %s\n", memfilename); end @@ -643,7 +643,8 @@ module testbench; flop #(1) ResetDReg(clk, reset, resetD); assign resetEdge = ~reset & resetD; initial begin - LogFile = $psprintf("branch_%s%0d.log", `BPRED_TYPE, `BPRED_SIZE); + LogFile = "branch.log"; // will break some of Ross's research analysis scripts + //LogFile = $psprintf("branch_%s%0d.log", `BPRED_TYPE, `BPRED_SIZE); file = $fopen(LogFile, "w"); end always @(posedge clk) begin @@ -742,8 +743,7 @@ module DCacheFlushFSM integer i, j, k, l; always @(posedge clk) begin - if (start) begin #1 - #1 + if (start) begin for(i = 0; i < numlines; i++) begin for(j = 0; j < numways; j++) begin for(l = 0; l < cachesramwords; l++) begin From 163b05f1ce2a959e88b2976c224fa4be2b939cb5 Mon Sep 17 00:00:00 2001 From: David Harris Date: Mon, 22 May 2023 09:57:41 -0700 Subject: [PATCH 2/6] Removed force from branch predictor initialization --- testbench/testbench.sv | 22 +++++++--------------- 1 file changed, 7 insertions(+), 15 deletions(-) diff --git a/testbench/testbench.sv b/testbench/testbench.sv index 0c8245948..f4766f5c2 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -252,7 +252,7 @@ module testbench; $readmemh(romfilename, dut.uncore.uncore.bootrom.bootrom.memory.ROM); $readmemh(sdcfilename, sdcard.sdcard.FLASHmem); // force sdc timers - force dut.uncore.uncore.sdc.SDC.LimitTimers = 1; + dut.uncore.uncore.sdc.SDC.LimitTimers = 1; end else begin if (`IROM_SUPPORTED) $readmemh(memfilename, dut.core.ifu.irom.irom.rom.ROM); else if (`BUS_SUPPORTED) $readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM); @@ -536,23 +536,15 @@ module testbench; if (`BPRED_SUPPORTED) begin integer adrindex; - always @(*) begin - if(reset) begin - for(adrindex = 0; adrindex < 2**`BTB_SIZE; adrindex++) begin - force dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[adrindex] = 0; + // initialize branch predictor on reset + always @(posedge reset) begin + for(adrindex = 0; adrindex < 2**`BTB_SIZE; adrindex++) begin + dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[adrindex] = 0; end for(adrindex = 0; adrindex < 2**`BPRED_SIZE; adrindex++) begin - force dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem[adrindex] = 0; + dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem[adrindex] = 0; end - #1; - for(adrindex = 0; adrindex < 2**`BTB_SIZE; adrindex++) begin - release dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[adrindex]; - end - for(adrindex = 0; adrindex < 2**`BPRED_SIZE; adrindex++) begin - release dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem[adrindex]; - end - end - end + end end From 21569b0a3bfb48c603a0c230faaa8244061e3406 Mon Sep 17 00:00:00 2001 From: David Harris Date: Mon, 22 May 2023 10:30:39 -0700 Subject: [PATCH 3/6] Verilate start --- sim/verilate | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) create mode 100755 sim/verilate diff --git a/sim/verilate b/sim/verilate new file mode 100755 index 000000000..345e17ab9 --- /dev/null +++ b/sim/verilate @@ -0,0 +1,22 @@ +#!/bin/bash +# simulate with Verilator + +export PATH=$PATH:/usr/local/bin/ +verilator=`which verilator` + +basepath=$(dirname $0)/.. +#for config in rv32e rv64gc rv32gc rv32imc rv32i rv64i rv64fpquad; do +for config in rv64gc; do + echo "$config linting..." + if !($verilator --cc "$@" --top-module testbench "-I$basepath/config/shared" "-I$basepath/config/$config" $basepath/testbench/testbench.sv $basepath/src/*/*.sv $basepath/src/*/*/*.sv --relative-includes ); then + echo "Exiting after $config lint due to errors or warnings" + exit 1 + fi +done +echo "All lints run with no errors or warnings" + +# --lint-only just runs lint rather than trying to compile and simulate +# -I points to the include directory where files such as `include wally-config.vh are found + +# For more exhaustive (and sometimes spurious) warnings, add --Wall to the Verilator command +# Unfortunately, this produces a bunch of UNUSED and UNDRIVEN signal warnings in blocks that are configured to not exist. From b4c9998b267bf699bccfc1a3bcac44f74d15714e Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 23 May 2023 15:37:09 -0700 Subject: [PATCH 4/6] Increased timeout for riscof because it is so slow --- tests/riscof/sail_cSim/riscof_sail_cSim.py | 3 ++- tests/riscof/spike/riscof_spike.py | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/tests/riscof/sail_cSim/riscof_sail_cSim.py b/tests/riscof/sail_cSim/riscof_sail_cSim.py index b34425f72..972b838e1 100644 --- a/tests/riscof/sail_cSim/riscof_sail_cSim.py +++ b/tests/riscof/sail_cSim/riscof_sail_cSim.py @@ -130,4 +130,5 @@ class sail_cSim(pluginTemplate): make.add_target(execute) # make.execute_all(self.work_dir) # DH 7/26/22 increase timeout so sim will finish on slow machines - make.execute_all(self.work_dir, timeout = 1800) +# DH 5/17/23 increase timeout to 3600 seconds + make.execute_all(self.work_dir, timeout = 3600) diff --git a/tests/riscof/spike/riscof_spike.py b/tests/riscof/spike/riscof_spike.py index 67c88b6ab..4a5b68b96 100644 --- a/tests/riscof/spike/riscof_spike.py +++ b/tests/riscof/spike/riscof_spike.py @@ -191,7 +191,8 @@ class spike(pluginTemplate): # parallel using the make command set above. #make.execute_all(self.work_dir) # DH 7/26/22 increase timeout to 1800 seconds so sim will finish on slow machines - make.execute_all(self.work_dir, timeout = 1800) + # DH 5/17/23 increase timeout to 3600 seconds + make.execute_all(self.work_dir, timeout = 3600) # if target runs are not required then we simply exit as this point after running all From 59020e6ef635ac82eff0cc0ea7476e7effb1c6c6 Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 23 May 2023 15:43:11 -0700 Subject: [PATCH 5/6] Removed unnecessary imperas tests from coverage --- sim/regression-wally | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/sim/regression-wally b/sim/regression-wally index 6e7ccf388..1569abd77 100755 --- a/sim/regression-wally +++ b/sim/regression-wally @@ -136,11 +136,9 @@ tests64gc = ["arch64f", "arch64d", "arch64f_fma", "arch64d_fma", "arch64i", "arc "arch64priv", "arch64c", "arch64m", "arch64zi", "wally64a", "wally64periph", "wally64priv"] if (coverage): # delete all but 64gc tests when running coverage configs = [] -# tests64gc = ["coverage64gc", "arch64f", "arch64d", "arch64i", "arch64priv", "arch64c", "arch64m", tests64gc = ["coverage64gc", "arch64i", "arch64priv", "arch64c", "arch64m", "arch64zi", "wally64a", "wally64periph", "wally64priv", - "arch64zba", "arch64zbb", "arch64zbc", "arch64zbs", - "imperas64f", "imperas64d", "imperas64c", "imperas64i"] + "arch64zba", "arch64zbb", "arch64zbc", "arch64zbs"] if (fp): tests64gc.append("arch64f") tests64gc.append("arch64d") From 9d74cad845f1932f3143a04a8379fe878fa5e5aa Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 23 May 2023 15:45:32 -0700 Subject: [PATCH 6/6] Added fulladder coverage script example --- examples/verilog/fulladder/fulladder-batch-coverage.do | 8 ++++++++ 1 file changed, 8 insertions(+) create mode 100644 examples/verilog/fulladder/fulladder-batch-coverage.do diff --git a/examples/verilog/fulladder/fulladder-batch-coverage.do b/examples/verilog/fulladder/fulladder-batch-coverage.do new file mode 100644 index 000000000..324ac9142 --- /dev/null +++ b/examples/verilog/fulladder/fulladder-batch-coverage.do @@ -0,0 +1,8 @@ +# fulladder-batch-coverage.do +# David_Harris@hmc.edu 22 May 2023 +vlog fulladder.sv +vopt +acc work.testbench -o workopt +cover=sbecf +vsim workopt -coverage +run -all +coverage save -instance /testbench/dut fulladder.ucdb +quit \ No newline at end of file