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Fixed icache pcmux control for handling miss spill miss.

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This commit is contained in:
Ross Thompson 2021-05-04 11:05:01 -05:00
parent 192878b124
commit 87d3869a6e
1 changed files with 1 additions and 1 deletions
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wally-pipelined/src/ifu/icache.sv
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@ -284,7 +284,7 @@ module icachecontroller #(parameter LINESIZE = 256) (
NextState = STATE_MISS_FETCH_WDV; NextState = STATE_MISS_FETCH_WDV;
end else if (~hit & spill) begin end else if (~hit & spill) begin
CntReset = 1'b1; CntReset = 1'b1;
PCMux = 2'b10; PCMux = 2'b01;
NextState = STATE_MISS_SPILL_FETCH_WDV; NextState = STATE_MISS_SPILL_FETCH_WDV;
end else begin end else begin
NextState = STATE_READY; NextState = STATE_READY;