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Incorporated Kunlin's Verilator hack so testbench runs 110x faster. Isolated within ifdef VERILATOR to make it easier to remove when Verilator issue 4967 is resolved

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David Harris 2024-04-03 07:23:02 -07:00
parent 8741b01818
commit 8755966f50
1 changed files with 16 additions and 5 deletions
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testbench/testbench.sv
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@ -319,8 +319,8 @@ module testbench;
// modifications 4/3/24 kunlin & harris to speed up Verilator // modifications 4/3/24 kunlin & harris to speed up Verilator
// For some reason, Verilator runs ~100x slower when these SelectTest and Validate codes are in the posedge clk block // For some reason, Verilator runs ~100x slower when these SelectTest and Validate codes are in the posedge clk block
end // added //end // added
always @(posedge SelectTest) // added //always @(posedge SelectTest) // added
if(SelectTest) begin if(SelectTest) begin
if (riscofTest) memfilename = {pathname, tests[test], "/ref/ref.elf.memfile"}; if (riscofTest) memfilename = {pathname, tests[test], "/ref/ref.elf.memfile"};
else if(TEST == "buildroot") begin else if(TEST == "buildroot") begin
@ -343,8 +343,14 @@ module testbench;
// and initialize them to zero (also initilaize them to zero at the start of the next test) // and initialize them to zero (also initilaize them to zero at the start of the next test)
updateProgramAddrLabelArray(ProgramAddrMapFile, ProgramLabelMapFile, ProgramAddrLabelArray); updateProgramAddrLabelArray(ProgramAddrMapFile, ProgramLabelMapFile, ProgramAddrLabelArray);
end end
`ifdef VERILATOR // this macro is defined when verilator is used
// Simulator Verilator has an issue that the validate logic below slows runtime 110x if it is
// in the posedge clk block rather than a separate posedge Validate block.
// Until it is fixed, provide a silly posedge Validate block to keep Verilator happy.
// https://github.com/verilator/verilator/issues/4967
end // restored
always @(posedge Validate) // added always @(posedge Validate) // added
`endif
if(Validate) begin if(Validate) begin
if (TEST == "embench") begin if (TEST == "embench") begin
// Writes contents of begin_signature to .sim.output file // Writes contents of begin_signature to .sim.output file
@ -381,13 +387,16 @@ module testbench;
if (totalerrors == 0) $display("SUCCESS! All tests ran without failures."); if (totalerrors == 0) $display("SUCCESS! All tests ran without failures.");
else $display("FAIL: %d test programs had errors", totalerrors); else $display("FAIL: %d test programs had errors", totalerrors);
`ifdef VERILATOR // this macro is defined when verilator is used `ifdef VERILATOR // this macro is defined when verilator is used
$finish; // V'lator needs $finish to terminate simulation. $finish; // Simulator Verilator needs $finish to terminate simulation.
`else `else
$stop; // if this is changed to $finish for Questa, wally-batch.do does not go to the next step to run coverage, and wally.do terminates without allowing GUI debug $stop; // if this is changed to $finish for Questa, wally-batch.do does not go to the next step to run coverage, and wally.do terminates without allowing GUI debug
`endif `endif
end end
end end
// end // removed `ifndef VERILATOR
// Remove this when issue 4967 is resolved and the posedge Validate logic above is removed
end
`endif
//////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////////
@ -767,6 +776,8 @@ end
string signame; string signame;
logic [P.XLEN-1:0] testadr, testadrNoBase; logic [P.XLEN-1:0] testadr, testadrNoBase;
//$display("Invoking CheckSignature %s %s %0t", pathname, TestName, $time);
// read .signature.output file and compare to check for errors // read .signature.output file and compare to check for errors
if (riscofTest) signame = {pathname, TestName, "/ref/Reference-sail_c_simulator.signature"}; if (riscofTest) signame = {pathname, TestName, "/ref/Reference-sail_c_simulator.signature"};
else signame = {pathname, TestName, ".signature.output"}; else signame = {pathname, TestName, ".signature.output"};