diff --git a/fpga/constraints/constraints-ArtyA7.xdc b/fpga/constraints/constraints-ArtyA7.xdc index 4dadf3987..7eb3598f5 100644 --- a/fpga/constraints/constraints-ArtyA7.xdc +++ b/fpga/constraints/constraints-ArtyA7.xdc @@ -7,34 +7,34 @@ create_generated_clock -name SPISDCClock -source [get_pins clk_out3_xlnx_mmcm] -multiply_by 1 -divide_by 1 [get_pins wallypipelinedsoc/uncore.uncore/sdc.sdc/SPICLK] ##### clock ##### -set_property PACKAGE_PIN E3 [get_ports {default_100mhz_clk}] -set_property IOSTANDARD LVCMOS33 [get_ports {default_100mhz_clk}] +set_property PACKAGE_PIN E3 [get_ports default_100mhz_clk] +set_property IOSTANDARD LVCMOS33 [get_ports default_100mhz_clk] ##### RVVI Ethernet #### # taken from https://github.com/alexforencich/verilog-ethernet/blob/master/example/Arty/fpga/fpga.xdc -set_property -dict {LOC F15 IOSTANDARD LVCMOS33} [get_ports phy_rx_clk] -set_property -dict {LOC D18 IOSTANDARD LVCMOS33} [get_ports {phy_rxd[0]}] -set_property -dict {LOC E17 IOSTANDARD LVCMOS33} [get_ports {phy_rxd[1]}] -set_property -dict {LOC E18 IOSTANDARD LVCMOS33} [get_ports {phy_rxd[2]}] -set_property -dict {LOC G17 IOSTANDARD LVCMOS33} [get_ports {phy_rxd[3]}] -set_property -dict {LOC G16 IOSTANDARD LVCMOS33} [get_ports phy_rx_dv] -set_property -dict {LOC C17 IOSTANDARD LVCMOS33} [get_ports phy_rx_er] -set_property -dict {LOC H16 IOSTANDARD LVCMOS33} [get_ports phy_tx_clk] -set_property -dict {LOC H14 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports {phy_txd[0]}] -set_property -dict {LOC J14 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports {phy_txd[1]}] -set_property -dict {LOC J13 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports {phy_txd[2]}] -set_property -dict {LOC H17 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports {phy_txd[3]}] -set_property -dict {LOC H15 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports phy_tx_en] -set_property -dict {LOC D17 IOSTANDARD LVCMOS33} [get_ports phy_col] -set_property -dict {LOC G14 IOSTANDARD LVCMOS33} [get_ports phy_crs] -set_property -dict {LOC G18 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports phy_ref_clk] -set_property -dict {LOC C16 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports phy_reset_n] +set_property -dict {LOC F15 IOSTANDARD LVCMOS33} [get_ports phy_rx_clk] +set_property -dict {LOC D18 IOSTANDARD LVCMOS33} [get_ports {phy_rxd[0]}] +set_property -dict {LOC E17 IOSTANDARD LVCMOS33} [get_ports {phy_rxd[1]}] +set_property -dict {LOC E18 IOSTANDARD LVCMOS33} [get_ports {phy_rxd[2]}] +set_property -dict {LOC G17 IOSTANDARD LVCMOS33} [get_ports {phy_rxd[3]}] +set_property -dict {LOC G16 IOSTANDARD LVCMOS33} [get_ports phy_rx_dv] +set_property -dict {LOC C17 IOSTANDARD LVCMOS33} [get_ports phy_rx_er] +set_property -dict {LOC H16 IOSTANDARD LVCMOS33} [get_ports phy_tx_clk] +set_property -dict {LOC H14 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports {phy_txd[0]}] +set_property -dict {LOC J14 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports {phy_txd[1]}] +set_property -dict {LOC J13 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports {phy_txd[2]}] +set_property -dict {LOC H17 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports {phy_txd[3]}] +set_property -dict {LOC H15 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports phy_tx_en] +set_property -dict {LOC D17 IOSTANDARD LVCMOS33} [get_ports phy_col] +set_property -dict {LOC G14 IOSTANDARD LVCMOS33} [get_ports phy_crs] +set_property -dict {LOC G18 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports phy_ref_clk] +set_property -dict {LOC C16 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports phy_reset_n] create_clock -period 40.000 -name phy_rx_clk [get_ports phy_rx_clk] create_clock -period 40.000 -name phy_tx_clk [get_ports phy_tx_clk] set_false_path -to [get_ports {phy_ref_clk phy_reset_n}] -set_output_delay 0 [get_ports {phy_ref_clk phy_reset_n}] +set_output_delay 0.000 [get_ports {phy_ref_clk phy_reset_n}] ##### GPI #### set_property PACKAGE_PIN A8 [get_ports {GPI[0]}] @@ -87,16 +87,16 @@ set_input_delay -clock [get_clocks clk_out3_xlnx_mmcm] -min -add_delay 2.000 [ge set_input_delay -clock [get_clocks clk_out3_xlnx_mmcm] -max -add_delay 2.000 [get_ports resetn] set_max_delay -from [get_ports resetn] 20.000 set_false_path -from [get_ports resetn] -set_property PACKAGE_PIN C2 [get_ports {resetn}] -set_property IOSTANDARD LVCMOS33 [get_ports {resetn}] +set_property PACKAGE_PIN C2 [get_ports resetn] +set_property IOSTANDARD LVCMOS33 [get_ports resetn] set_input_delay -clock [get_clocks clk_out3_xlnx_mmcm] -min -add_delay 2.000 [get_ports south_reset] set_input_delay -clock [get_clocks clk_out3_xlnx_mmcm] -max -add_delay 2.000 [get_ports south_reset] set_max_delay -from [get_ports south_reset] 20.000 set_false_path -from [get_ports south_reset] -set_property PACKAGE_PIN D9 [get_ports {south_reset}] -set_property IOSTANDARD LVCMOS33 [get_ports {south_reset}] +set_property PACKAGE_PIN D9 [get_ports south_reset] +set_property IOSTANDARD LVCMOS33 [get_ports south_reset] @@ -125,15 +125,27 @@ set_property IOSTANDARD LVCMOS33 [get_ports {south_reset}] #set_property PULLUP true [get_ports {SDCCD}] # SDCDat[3] -set_property -dict {PACKAGE_PIN D4 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {SDCCS}] +set_property PACKAGE_PIN D4 [get_ports SDCCS] +set_property IOSTANDARD LVCMOS33 [get_ports SDCCS] +set_property PULLTYPE PULLUP [get_ports SDCCS] # set_property -dict {PACKAGE_PIN D2 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {SDCDat[2]}] # set_property -dict {PACKAGE_PIN E2 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {SDCDat[1]}] # SDCDat[0] -set_property -dict {PACKAGE_PIN F4 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {SDCIn}] -set_property -dict {PACKAGE_PIN F3 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {SDCCLK}] -set_property -dict {PACKAGE_PIN D3 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {SDCCmd}] -set_property -dict {PACKAGE_PIN H2 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {SDCCD}] -set_property -dict {PACKAGE_PIN G2 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {SDCWP}] +set_property PACKAGE_PIN F4 [get_ports SDCIn] +set_property IOSTANDARD LVCMOS33 [get_ports SDCIn] +set_property PULLTYPE PULLUP [get_ports SDCIn] +set_property PACKAGE_PIN F3 [get_ports SDCCLK] +set_property IOSTANDARD LVCMOS33 [get_ports SDCCLK] +set_property PULLTYPE PULLUP [get_ports SDCCLK] +set_property PACKAGE_PIN D3 [get_ports SDCCmd] +set_property IOSTANDARD LVCMOS33 [get_ports SDCCmd] +set_property PULLTYPE PULLUP [get_ports SDCCmd] +set_property PACKAGE_PIN H2 [get_ports SDCCD] +set_property IOSTANDARD LVCMOS33 [get_ports SDCCD] +set_property PULLTYPE PULLUP [get_ports SDCCD] +set_property PACKAGE_PIN G2 [get_ports SDCWP] +set_property IOSTANDARD LVCMOS33 [get_ports SDCWP] +set_property PULLTYPE PULLUP [get_ports SDCWP] set_output_delay -clock [get_clocks SPISDCClock] -min -add_delay 2.500 [get_ports {SDCCS}] @@ -158,54 +170,54 @@ set_max_delay -datapath_only -from [get_pins xlnx_ddr3_c0/u_xlnx_ddr3_mig/u_memc # ddr3 -set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[0]] -set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[1]] -set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[2]] -set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[3]] -set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[4]] -set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[5]] -set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[6]] -set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[7]] -set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[8]] -set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[9]] -set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[10]] -set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[11]] -set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[12]] -set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[13]] -set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[14]] -set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[15]] -set_property IOSTANDARD SSTL135 [get_ports ddr3_dm[0]] -set_property IOSTANDARD SSTL135 [get_ports ddr3_dm[1]] +set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[0]}] +set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[1]}] +set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[2]}] +set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[3]}] +set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[4]}] +set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[5]}] +set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[6]}] +set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[7]}] +set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[8]}] +set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[9]}] +set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[10]}] +set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[11]}] +set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[12]}] +set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[13]}] +set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[14]}] +set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[15]}] +set_property IOSTANDARD SSTL135 [get_ports {ddr3_dm[0]}] +set_property IOSTANDARD SSTL135 [get_ports {ddr3_dm[1]}] set_property IOSTANDARD DIFF [get_ports ddr3_dqs_p[0]] set_property IOSTANDARD DIFF [get_ports ddr3_dqs_n[0]] set_property IOSTANDARD DIFF [get_ports ddr3_dqs_p[1]] set_property IOSTANDARD DIFF [get_ports ddr3_dqs_n[1]] -set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[13]] -set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[12]] -set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[11]] -set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[10]] -set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[9]] -set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[8]] -set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[7]] -set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[6]] -set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[5]] -set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[4]] -set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[3]] -set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[2]] -set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[1]] -set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[0]] -set_property IOSTANDARD SSTL135 [get_ports ddr3_ba[2]] -set_property IOSTANDARD SSTL135 [get_ports ddr3_ba[1]] -set_property IOSTANDARD SSTL135 [get_ports ddr3_ba[0]] +set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[13]}] +set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[12]}] +set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[11]}] +set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[10]}] +set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[9]}] +set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[8]}] +set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[7]}] +set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[6]}] +set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[5]}] +set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[4]}] +set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[3]}] +set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[2]}] +set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[1]}] +set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[0]}] +set_property IOSTANDARD SSTL135 [get_ports {ddr3_ba[2]}] +set_property IOSTANDARD SSTL135 [get_ports {ddr3_ba[1]}] +set_property IOSTANDARD SSTL135 [get_ports {ddr3_ba[0]}] set_property IOSTANDARD DIFF [get_ports ddr3_ck_p[0]] set_property IOSTANDARD DIFF [get_ports ddr3_ck_n[0]] set_property IOSTANDARD SSTL135 [get_ports ddr3_ras_n] set_property IOSTANDARD SSTL135 [get_ports ddr3_cas_n] set_property IOSTANDARD SSTL135 [get_ports ddr3_we_n] set_property IOSTANDARD SSTL135 [get_ports ddr3_reset_n] -set_property IOSTANDARD SSTL135 [get_ports ddr3_cke[0]] -set_property IOSTANDARD SSTL135 [get_ports ddr3_odt[0]] -set_property IOSTANDARD SSTL135 [get_ports ddr3_cs_n[0]] +set_property IOSTANDARD SSTL135 [get_ports {ddr3_cke[0]}] +set_property IOSTANDARD SSTL135 [get_ports {ddr3_odt[0]}] +set_property IOSTANDARD SSTL135 [get_ports {ddr3_cs_n[0]}] set_properity PACKAGE_PIN K5 [get_ports ddr3_dq[0]] @@ -257,3 +269,28 @@ set_properity PACKAGE_PIN N5 [get_ports ddr3_cke[0]] set_properity PACKAGE_PIN R5 [get_ports ddr3_odt[0]] set_properity PACKAGE_PIN U8 [get_ports ddr3_cs_n[0]] + +create_clock -period 40.000 -name VIRTUAL_clk_out3_mmcm -waveform {0.000 20.000} +set_input_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -min -add_delay 10.000 [get_ports {GPI[*]}] +set_input_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -max -add_delay 10.000 [get_ports {GPI[*]}] +set_input_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -min -add_delay 10.000 [get_ports SDCCD] +set_input_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -max -add_delay 10.000 [get_ports SDCCD] +set_input_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -min -add_delay 10.000 [get_ports SDCIn] +set_input_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -max -add_delay 10.000 [get_ports SDCIn] +set_input_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -min -add_delay 10.000 [get_ports SDCWP] +set_input_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -max -add_delay 10.000 [get_ports SDCWP] +set_input_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -min -add_delay 10.000 [get_ports UARTSin] +set_input_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -max -add_delay 10.000 [get_ports UARTSin] +create_clock -period 12.000 -name VIRTUAL_clk_pll_i -waveform {0.000 6.000} +set_output_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -min -add_delay 0.000 [get_ports {GPO[*]}] +set_output_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -max -add_delay 10.000 [get_ports {GPO[*]}] +set_output_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -min -add_delay 0.000 [get_ports SDCCLK] +set_output_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -max -add_delay 0.000 [get_ports SDCCLK] +set_output_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -min -add_delay 0.000 [get_ports SDCCS] +set_output_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -max -add_delay 10.000 [get_ports SDCCS] +set_output_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -min -add_delay 0.000 [get_ports SDCCmd] +set_output_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -max -add_delay 10.000 [get_ports SDCCmd] +set_output_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -min -add_delay 0.000 [get_ports UARTSout] +set_output_delay -clock [get_clocks VIRTUAL_clk_out3_mmcm] -max -add_delay 10.000 [get_ports UARTSout] +#set_output_delay -clock [get_clocks VIRTUAL_clk_pll_i] -min -add_delay 0.000 [get_ports ddr3_reset_n] +#set_output_delay -clock [get_clocks VIRTUAL_clk_pll_i] -max -add_delay 80.000 [get_ports ddr3_reset_n] diff --git a/fpga/constraints/constraints-vcu108.xdc b/fpga/constraints/constraints-vcu108.xdc index 8d59509be..638cfb2a5 100644 --- a/fpga/constraints/constraints-vcu108.xdc +++ b/fpga/constraints/constraints-vcu108.xdc @@ -3,21 +3,22 @@ # mmcm_clkout0 is the clock output of the DDR4 memory interface / 4. # This clock is not used by wally or the AHBLite Bus. However it is used by the AXI BUS on the DD4 IP. -# create_generated_clock -name CLKDiv64_Gen -source [get_pins wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/I0] -multiply_by 1 -divide_by 2 [get_pins wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/O] -create_generated_clock -name CLKDiv64_Gen -source [get_pins xlnx_ddr4_c0/addn_ui_clkout1] -multiply_by 1 -divide_by 1 [get_pins axiSDC/clock_posedge_reg/Q] +# create_generated_clock -name CLKDiv64_Gen -source [get_pins #wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/I0] -multiply_by 1 -divide_by 2 [get_pins wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/O] +#create_generated_clock -name CLKDiv64_Gen -source [get_pins ddr4_c0/addn_ui_clkout1] -multiply_by 1 -divide_by 1 [get_pins axiSDC/clock_posedge_reg/Q] +create_generated_clock -name SPISDCClock -source [get_pins ddr4/addn_ui_clkout1] -multiply_by 1 -divide_by 1 [get_pins wallypipelinedsoc/uncore.uncore/sdc.sdc/SPICLK] ##### GPI #### set_property PACKAGE_PIN E34 [get_ports {GPI[0]}] set_property PACKAGE_PIN M22 [get_ports {GPI[1]}] set_property PACKAGE_PIN AW27 [get_ports {GPI[2]}] -set_property PACKAGE_PIN A10 [get_ports {GPI[3]}] -set_property IOSTANDARD LVCMOS12 [get_ports {GPI[3]}] +#set_property PACKAGE_PIN A10 [get_ports {GPI[3]}] +#set_property IOSTANDARD LVCMOS12 [get_ports {GPI[3]}] set_property IOSTANDARD LVCMOS12 [get_ports {GPI[2]}] set_property IOSTANDARD LVCMOS12 [get_ports {GPI[1]}] set_property IOSTANDARD LVCMOS12 [get_ports {GPI[0]}] set_input_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 2.000 [get_ports {GPI[*]}] set_input_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 2.000 [get_ports {GPI[*]}] -set_max_delay -from [get_ports {GPI[*]}] 10.000n +set_max_delay -from [get_ports {GPI[*]}] 10.000 ##### GPO #### set_property PACKAGE_PIN AT32 [get_ports {GPO[0]}] @@ -58,7 +59,7 @@ set_input_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_port set_input_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 0.000 [get_ports reset] set_max_delay -from [get_ports reset] 15.000 set_false_path -from [get_ports reset] -set_property PACKAGE_PIN E34 [get_ports {reset}] +set_property PACKAGE_PIN A10 [get_ports {reset}] set_property IOSTANDARD LVCMOS12 [get_ports {reset}] @@ -69,15 +70,6 @@ set_property IOSTANDARD LVCMOS12 [get_ports {cpu_reset}] set_output_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_ports {cpu_reset}] set_output_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 0.000 [get_ports {cpu_reset}] - -##### calib ##### -set_property PACKAGE_PIN BA37 [get_ports calib] -set_property IOSTANDARD LVCMOS12 [get_ports calib] -set_output_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_ports calib] -set_output_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 20.000 [get_ports calib] -set_max_delay -from [get_pins xlnx_ddr4_c0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/calDone_gated_reg/C] -to [get_ports calib] 50.000 - - ##### ahblite_resetn ##### set_property PACKAGE_PIN AV36 [get_ports {ahblite_resetn}] set_property IOSTANDARD LVCMOS12 [get_ports {ahblite_resetn}] @@ -94,44 +86,34 @@ set_input_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 2.000 [get_port ##### SD Card I/O ##### -# set_property PACKAGE_PIN BC14 [get_ports {SDCDat[3]}] -# set_property IOSTANDARD LVCMOS18 [get_ports {SDCDat[3]}] -# set_property IOSTANDARD LVCMOS18 [get_ports {SDCDat[2]}] -# set_property IOSTANDARD LVCMOS18 [get_ports {SDCDat[1]}] -# set_property IOSTANDARD LVCMOS18 [get_ports {SDCDat[0]}] -# set_property PACKAGE_PIN BF7 [get_ports {SDCDat[2]}] -# set_property PACKAGE_PIN BC13 [get_ports {SDCDat[1]}] -# set_property PACKAGE_PIN AW16 [get_ports {SDCDat[0]}] -# set_property IOSTANDARD LVCMOS18 [get_ports SDCCLK] -# set_property IOSTANDARD LVCMOS18 [get_ports {SDCCmd}] -# set_property PACKAGE_PIN BB16 [get_ports SDCCLK] -# set_property PACKAGE_PIN BA10 [get_ports {SDCCmd}] -# set_property PULLUP true [get_ports {SDCDat[3]}] -# set_property PULLUP true [get_ports {SDCDat[2]}] -# set_property PULLUP true [get_ports {SDCDat[1]}] -# set_property PULLUP true [get_ports {SDCDat[0]}] -# set_property PULLUP true [get_ports {SDCCmd}] +set_output_delay -clock [get_clocks SPISDCClock] -min -add_delay 2.500 [get_ports {SDCCS}] +set_output_delay -clock [get_clocks SPISDCClock] -max -add_delay 10.000 [get_ports {SDCCS}] +set_input_delay -clock [get_clocks SPISDCClock] -min -add_delay 2.500 [get_ports {SDCIn}] +set_input_delay -clock [get_clocks SPISDCClock] -max -add_delay 10.000 [get_ports {SDCIn}] +set_output_delay -clock [get_clocks SPISDCClock] -min -add_delay 2.000 [get_ports {SDCCmd}] +set_output_delay -clock [get_clocks SPISDCClock] -max -add_delay 6.000 [get_ports {SDCCmd}] +set_output_delay -clock [get_clocks SPISDCClock] 0.000 [get_ports SDCCLK] -set_property -dict {PACKAGE_PIN BC14 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {SDCDat[3]}] -set_property -dict {PACKAGE_PIN BF7 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {SDCDat[2]}] -set_property -dict {PACKAGE_PIN BC13 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {SDCDat[1]}] -set_property -dict {PACKAGE_PIN AW16 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {SDCDat[0]}] +set_property -dict {PACKAGE_PIN BC14 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {SDCCS}] +set_property -dict {PACKAGE_PIN AW16 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {SDCIn}] set_property -dict {PACKAGE_PIN BA10 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {SDCCmd}] set_property -dict {PACKAGE_PIN AW12 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {SDCCD}] set_property -dict {PACKAGE_PIN BB16 IOSTANDARD LVCMOS18} [get_ports SDCCLK] +set_property PACKAGE_PIN AW12 [get_ports SDCCD] +set_property IOSTANDARD LVCMOS18 [get_ports SDCCD] +set_property PULLTYPE PULLUP [get_ports SDCCD] +set_property PACKAGE_PIN BC16 [get_ports SDCWP] +set_property IOSTANDARD LVCMOS18 [get_ports SDCWP] +set_property PULLTYPE PULLUP [get_ports SDCWP] -set_input_delay -clock [get_clocks CLKDiv64_Gen] -min -add_delay 2.500 [get_ports {SDCDat[*]}] -set_input_delay -clock [get_clocks CLKDiv64_Gen] -max -add_delay 21.000 [get_ports {SDCDat[*]}] - -set_input_delay -clock [get_clocks CLKDiv64_Gen] -min -add_delay 2.500 [get_ports {SDCCmd}] -set_input_delay -clock [get_clocks CLKDiv64_Gen] -max -add_delay 14.000 [get_ports {SDCCmd}] - - -set_output_delay -clock [get_clocks CLKDiv64_Gen] -min -add_delay 2.000 [get_ports {SDCCmd}] -set_output_delay -clock [get_clocks CLKDiv64_Gen] -max -add_delay 6.000 [get_ports {SDCCmd}] - -set_output_delay -clock [get_clocks CLKDiv64_Gen] 0.000 [get_ports SDCCLK] +#set_input_delay -clock [get_clocks CLKDiv64_Gen] -min -add_delay 2.500 [get_ports {SDCDat[*]}] +#set_input_delay -clock [get_clocks CLKDiv64_Gen] -max -add_delay 21.000 [get_ports {SDCDat[*]}] +#set_input_delay -clock [get_clocks CLKDiv64_Gen] -min -add_delay 2.500 [get_ports {SDCCmd}] +#set_input_delay -clock [get_clocks CLKDiv64_Gen] -max -add_delay 14.000 [get_ports {SDCCmd}] +#set_output_delay -clock [get_clocks CLKDiv64_Gen] -min -add_delay 2.000 [get_ports {SDCCmd}] +#set_output_delay -clock [get_clocks CLKDiv64_Gen] -max -add_delay 6.000 [get_ports {SDCCmd}] +#set_output_delay -clock [get_clocks CLKDiv64_Gen] 0.000 [get_ports SDCCLK] @@ -264,8 +246,8 @@ set_property PACKAGE_PIN D27 [get_ports {c0_ddr4_dm_dbi_n[7]}] set_max_delay -datapath_only -from [get_pins xlnx_ddr4_c0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/calDone_gated_reg/C] -to [get_pins xlnx_proc_sys_reset_0/U0/EXT_LPF/lpf_int_reg/D] 10.000 -set_output_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_ports c0_ddr4_reset_n] -set_output_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 20.000 [get_ports c0_ddr4_reset_n] +#set_output_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_ports c0_ddr4_reset_n] +#set_output_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 20.000 [get_ports c0_ddr4_reset_n] diff --git a/fpga/constraints/marked_debug.txt b/fpga/constraints/marked_debug.txt index afed3dd23..1d23c29a2 100644 --- a/fpga/constraints/marked_debug.txt +++ b/fpga/constraints/marked_debug.txt @@ -3,8 +3,5 @@ wally/wallypipelinedcore.sv: logic TrapM wally/wallypipelinedcore.sv: logic InstrValidM wally/wallypipelinedcore.sv: logic InstrM lsu/lsu.sv: logic IEUAdrM -lsu/lsu.sv: logic PAdrM -lsu/lsu.sv: logic ReadDataM -lsu/lsu.sv: logic WriteDataM lsu/lsu.sv: logic MemRWM -privileged/csrc.sv: logic HPMCOUNTER_REGW +mmu/hptw.sv: logic SATP_REGW diff --git a/fpga/constraints/marked_debug_rvvi.txt b/fpga/constraints/marked_debug_rvvi.txt new file mode 100644 index 000000000..afed3dd23 --- /dev/null +++ b/fpga/constraints/marked_debug_rvvi.txt @@ -0,0 +1,10 @@ +wally/wallypipelinedcore.sv: logic PCM +wally/wallypipelinedcore.sv: logic TrapM +wally/wallypipelinedcore.sv: logic InstrValidM +wally/wallypipelinedcore.sv: logic InstrM +lsu/lsu.sv: logic IEUAdrM +lsu/lsu.sv: logic PAdrM +lsu/lsu.sv: logic ReadDataM +lsu/lsu.sv: logic WriteDataM +lsu/lsu.sv: logic MemRWM +privileged/csrc.sv: logic HPMCOUNTER_REGW diff --git a/fpga/constraints/vcu-small-debug.xdc b/fpga/constraints/vcu-small-debug.xdc index 62fea508f..0ce1152f3 100644 --- a/fpga/constraints/vcu-small-debug.xdc +++ b/fpga/constraints/vcu-small-debug.xdc @@ -1,6 +1,6 @@ create_debug_core u_ila_0 ila -set_property C_DATA_DEPTH 2048 [get_debug_cores u_ila_0] +set_property C_DATA_DEPTH 8192 [get_debug_cores u_ila_0] set_property C_TRIGIN_EN false [get_debug_cores u_ila_0] set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0] set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0] diff --git a/fpga/generator/Makefile b/fpga/generator/Makefile index 3f33d55dd..1d0fcc6bc 100644 --- a/fpga/generator/Makefile +++ b/fpga/generator/Makefile @@ -27,19 +27,15 @@ FPGA_VCU: PreProcessFiles IP_VCU # Generate IP Blocks .PHONY: IP_Arty IP_VCU -IP_VCU: $(dst)/xlnx_proc_sys_reset.log \ +IP_VCU: $(dst)/sysrst.log \ MEM_VCU \ - $(dst)/xlnx_axi_clock_converter.log \ - $(dst)/xlnx_ahblite_axi_bridge.log \ - $(dst)/xlnx_axi_crossbar.log \ - $(dst)/xlnx_axi_dwidth_conv_32to64.log \ - $(dst)/xlnx_axi_dwidth_conv_64to32.log \ - $(dst)/xlnx_axi_prtcl_conv.log -IP_Arty: $(dst)/xlnx_proc_sys_reset.log \ + $(dst)/clkconverter.log \ + $(dst)/ahbaxibridge.log +IP_Arty: $(dst)/sysrst.log \ MEM_Arty \ $(dst)/xlnx_mmcm.log \ - $(dst)/xlnx_axi_clock_converter.log \ - $(dst)/xlnx_ahblite_axi_bridge.log + $(dst)/clkconverter.log \ + $(dst)/ahbaxibridge.log #$(dst)/xlnx_axi_crossbar.log \ #$(dst)/xlnx_axi_dwidth_conv_32to64.log \ #$(dst)/xlnx_axi_dwidth_conv_64to32.log \ @@ -48,9 +44,9 @@ IP_Arty: $(dst)/xlnx_proc_sys_reset.log \ # Generate Memory IP Blocks .PHONY: MEM_VCU MEM_Arty MEM_VCU: - $(MAKE) $(dst)/xlnx_ddr4-$(board).log + $(MAKE) $(dst)/ddr4-$(board).log MEM_Arty: - $(MAKE) $(dst)/xlnx_ddr3-$(board).log + $(MAKE) $(dst)/ddr3-$(board).log # Copy files and make necessary modifications .PHONY: PreProcessFiles diff --git a/fpga/generator/xlnx_ahblite_axi_bridge.tcl b/fpga/generator/ahbaxibridge.tcl similarity index 78% rename from fpga/generator/xlnx_ahblite_axi_bridge.tcl rename to fpga/generator/ahbaxibridge.tcl index 946e23174..e41eed6ce 100644 --- a/fpga/generator/xlnx_ahblite_axi_bridge.tcl +++ b/fpga/generator/ahbaxibridge.tcl @@ -2,15 +2,7 @@ set partNumber $::env(XILINX_PART) set boardName $::env(XILINX_BOARD) -# vcu118 board -#set partNumber xcvu9p-flga2104-2L-e -#set boardName xilinx.com:vcu118:part0:2.4 - -# kcu105 board -#set partNumber xcku040-ffva1156-2-e -#set boardName xilinx.com:kcu105:part0:1.7 - -set ipName xlnx_ahblite_axi_bridge +set ipName ahbaxibridge create_project $ipName . -force -part $partNumber if {$boardName!="ArtyA7"} { diff --git a/fpga/generator/xlnx_axi_clock_converter.tcl b/fpga/generator/clkconverter.tcl similarity index 96% rename from fpga/generator/xlnx_axi_clock_converter.tcl rename to fpga/generator/clkconverter.tcl index 87a199cb7..6a9746504 100644 --- a/fpga/generator/xlnx_axi_clock_converter.tcl +++ b/fpga/generator/clkconverter.tcl @@ -4,7 +4,7 @@ set boardName $::env(XILINX_BOARD) #set partNumber xcvu9p-flga2104-2L-e #set boardName xilinx.com:vcu118:part0:2.4 -set ipName xlnx_axi_clock_converter +set ipName clkconverter create_project $ipName . -force -part $partNumber if {$boardName!="ArtyA7"} { diff --git a/fpga/generator/xlnx_ddr3-ArtyA7.tcl b/fpga/generator/ddr3-ArtyA7.tcl similarity index 97% rename from fpga/generator/xlnx_ddr3-ArtyA7.tcl rename to fpga/generator/ddr3-ArtyA7.tcl index 2213e7da9..20aed4e9f 100644 --- a/fpga/generator/xlnx_ddr3-ArtyA7.tcl +++ b/fpga/generator/ddr3-ArtyA7.tcl @@ -2,7 +2,7 @@ set partNumber $::env(XILINX_PART) set boardName $::env(XILINX_BOARD) -set ipName xlnx_ddr3 +set ipName ddr3 create_project $ipName . -force -part $partNumber set_property board_part $boardName [current_project] diff --git a/fpga/generator/xlnx_ddr4-vcu108.tcl b/fpga/generator/ddr4-vcu108.tcl similarity index 93% rename from fpga/generator/xlnx_ddr4-vcu108.tcl rename to fpga/generator/ddr4-vcu108.tcl index 71f8f06a4..63c849729 100644 --- a/fpga/generator/xlnx_ddr4-vcu108.tcl +++ b/fpga/generator/ddr4-vcu108.tcl @@ -4,7 +4,7 @@ set boardName $::env(XILINX_BOARD) #set partNumber xcvu9p-flga2104-2L-e #set boardName xilinx.com:vcu118:part0:2.4 -set ipName xlnx_ddr4 +set ipName ddr4 create_project $ipName . -force -part $partNumber set_property board_part $boardName [current_project] @@ -15,12 +15,12 @@ set_property -dict [list CONFIG.C0.ControllerType {DDR4_SDRAM} \ CONFIG.No_Controller {1} \ CONFIG.Phy_Only {Complete_Memory_Controller} \ CONFIG.C0.DDR4_PhyClockRatio {4:1} \ - CONFIG.C0.DDR4_TimePeriod {1200} \ + CONFIG.C0.DDR4_TimePeriod {833} \ CONFIG.C0.DDR4_MemoryPart {MT40A256M16GE-083E} \ CONFIG.C0.DDR4_BurstLength {8} \ CONFIG.C0.DDR4_BurstType {Sequential} \ - CONFIG.C0.DDR4_CasLatency {13} \ - CONFIG.C0.DDR4_CasWriteLatency {10} \ + CONFIG.C0.DDR4_CasLatency {16} \ + CONFIG.C0.DDR4_CasWriteLatency {12} \ CONFIG.C0.DDR4_Slot {Single} \ CONFIG.C0.DDR4_MemoryVoltage {1.2V} \ CONFIG.C0.DDR4_DataWidth {64} \ @@ -36,14 +36,11 @@ set_property -dict [list CONFIG.C0.ControllerType {DDR4_SDRAM} \ CONFIG.C0.DDR4_AxiIDWidth {4} \ CONFIG.C0.DDR4_AxiAddressWidth {31} \ CONFIG.C0.DDR4_AxiNarrowBurst {false} \ - CONFIG.C0.DDR4_CLKFBOUT_MULT {5} \ - CONFIG.C0.DDR4_DIVCLK_DIVIDE {1} \ - CONFIG.C0.DDR4_CLKOUT0_DIVIDE {6} \ CONFIG.Reference_Clock {Differential} \ CONFIG.ADDN_UI_CLKOUT1.INSERT_VIP {0} \ - CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {22} \ + CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {50} \ CONFIG.ADDN_UI_CLKOUT2.INSERT_VIP {0} \ - CONFIG.ADDN_UI_CLKOUT2_FREQ_HZ {208} \ + CONFIG.ADDN_UI_CLKOUT2_FREQ_HZ {300} \ CONFIG.ADDN_UI_CLKOUT3.INSERT_VIP {0} \ CONFIG.ADDN_UI_CLKOUT3_FREQ_HZ {None} \ CONFIG.ADDN_UI_CLKOUT4.INSERT_VIP {0} \ @@ -106,7 +103,7 @@ set_property -dict [list CONFIG.C0.ControllerType {DDR4_SDRAM} \ CONFIG.C0.DDR4_CustomParts {no_file_loaded} \ CONFIG.C0.DDR4_EN_PARITY {false} \ CONFIG.C0.DDR4_Enable_LVAUX {false} \ - CONFIG.C0.DDR4_InputClockPeriod {3359} \ + CONFIG.C0.DDR4_InputClockPeriod {3332} \ CONFIG.C0.DDR4_LR_SKEW_0 {0} \ CONFIG.C0.DDR4_LR_SKEW_1 {0} \ CONFIG.C0.DDR4_MemoryName {MainMemory} \ @@ -115,6 +112,7 @@ set_property -dict [list CONFIG.C0.ControllerType {DDR4_SDRAM} \ CONFIG.C0.DDR4_ODT_SKEW_2 {0} \ CONFIG.C0.DDR4_ODT_SKEW_3 {0} \ CONFIG.C0.DDR4_OnDieTermination {RZQ/6} \ + CONFIG.C0.DDR4_OutputDriverImpedenceControl {RZQ/7} \ CONFIG.C0.DDR4_PAR_SKEW {0} \ CONFIG.C0.DDR4_Specify_MandD {false} \ CONFIG.C0.DDR4_TREFI {0} \ diff --git a/fpga/generator/xlnx_ddr4-vcu118.tcl b/fpga/generator/ddr4-vcu118.tcl similarity index 99% rename from fpga/generator/xlnx_ddr4-vcu118.tcl rename to fpga/generator/ddr4-vcu118.tcl index 8041726ff..5a98c07de 100644 --- a/fpga/generator/xlnx_ddr4-vcu118.tcl +++ b/fpga/generator/ddr4-vcu118.tcl @@ -4,7 +4,7 @@ set boardName $::env(XILINX_BOARD) #set partNumber xcvu9p-flga2104-2L-e #set boardName xilinx.com:vcu118:part0:2.4 -set ipName xlnx_ddr4 +set ipName ddr4 create_project $ipName . -force -part $partNumber set_property board_part $boardName [current_project] diff --git a/fpga/generator/xlnx_mmcm.tcl b/fpga/generator/mmcm.tcl similarity index 93% rename from fpga/generator/xlnx_mmcm.tcl rename to fpga/generator/mmcm.tcl index 146a9cf41..de4a1a1d0 100644 --- a/fpga/generator/xlnx_mmcm.tcl +++ b/fpga/generator/mmcm.tcl @@ -1,7 +1,7 @@ set partNumber $::env(XILINX_PART) set boardName $::env(XILINX_BOARD) -set ipName xlnx_mmcm +set ipName mmcm create_project $ipName . -force -part $partNumber set_property board_part $boardName [current_project] @@ -15,7 +15,7 @@ set_property -dict [list CONFIG.PRIM_IN_FREQ {100.000} \ CONFIG.CLKOUT4_USED {true} \ CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {166.66667} \ CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {200} \ - CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {20} \ + CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {25} \ CONFIG.CLKOUT4_REQUESTED_OUT_FREQ {25} \ CONFIG.CLKIN1_JITTER_PS {10.0} \ ] [get_ips $ipName] diff --git a/fpga/generator/xlnx_proc_sys_reset.tcl b/fpga/generator/sysrst.tcl similarity index 96% rename from fpga/generator/xlnx_proc_sys_reset.tcl rename to fpga/generator/sysrst.tcl index 06ca4fb1f..8225c02d5 100644 --- a/fpga/generator/xlnx_proc_sys_reset.tcl +++ b/fpga/generator/sysrst.tcl @@ -4,7 +4,7 @@ set boardName $::env(XILINX_BOARD) #set partNumber xcvu9p-flga2104-2L-e #set boardName xilinx.com:vcu118:part0:2.4 -set ipName xlnx_proc_sys_reset +set ipName sysrst create_project $ipName . -force -part $partNumber if {$boardName!="ArtyA7"} { diff --git a/fpga/generator/wally.tcl b/fpga/generator/wally.tcl index a5e60a3d5..106345854 100644 --- a/fpga/generator/wally.tcl +++ b/fpga/generator/wally.tcl @@ -5,6 +5,11 @@ set boardName $::env(XILINX_BOARD) set boardSubName [lindex [split ${boardName} :] 1] set board $::env(board) +#set partNumber xc7a100tcsg324-1 +#set boardName digilentinc.com:arty-a7-100:part0:1.1 +#set boardSubName arty-a7-100 +#set board ArtyA7 + set ipName WallyFPGA create_project $ipName . -force -part $partNumber @@ -23,20 +28,15 @@ if {$board=="ArtyA7"} { } # read in ip -read_ip IP/xlnx_proc_sys_reset.srcs/sources_1/ip/xlnx_proc_sys_reset/xlnx_proc_sys_reset.xci -read_ip IP/xlnx_ahblite_axi_bridge.srcs/sources_1/ip/xlnx_ahblite_axi_bridge/xlnx_ahblite_axi_bridge.xci -read_ip IP/xlnx_axi_clock_converter.srcs/sources_1/ip/xlnx_axi_clock_converter/xlnx_axi_clock_converter.xci -# Added crossbar - Jacob Pease <2023-01-12 Thu> -#read_ip IP/xlnx_axi_crossbar.srcs/sources_1/ip/xlnx_axi_crossbar/xlnx_axi_crossbar.xci -#read_ip IP/xlnx_axi_dwidth_conv_32to64.srcs/sources_1/ip/xlnx_axi_dwidth_conv_32to64/xlnx_axi_dwidth_conv_32to64.xci -#read_ip IP/xlnx_axi_dwidth_conv_64to32.srcs/sources_1/ip/xlnx_axi_dwidth_conv_64to32/xlnx_axi_dwidth_conv_64to32.xci -#read_ip IP/xlnx_axi_prtcl_conv.srcs/sources_1/ip/xlnx_axi_prtcl_conv/xlnx_axi_prtcl_conv.xci +import_ip IP/sysrst.srcs/sources_1/ip/sysrst/sysrst.xci +import_ip IP/ahbaxibridge.srcs/sources_1/ip/ahbaxibridge/ahbaxibridge.xci +import_ip IP/clkconverter.srcs/sources_1/ip/clkconverter/clkconverter.xci if {$board=="ArtyA7"} { - read_ip IP/xlnx_ddr3.srcs/sources_1/ip/xlnx_ddr3/xlnx_ddr3.xci - read_ip IP/xlnx_mmcm.srcs/sources_1/ip/xlnx_mmcm/xlnx_mmcm.xci + import_ip IP/ddr3.srcs/sources_1/ip/ddr3/ddr3.xci + import_ip IP/mmcm.srcs/sources_1/ip/mmcm/mmcm.xci } else { - read_ip IP/xlnx_ddr4.srcs/sources_1/ip/xlnx_ddr4/xlnx_ddr4.xci + import_ip IP/ddr4.srcs/sources_1/ip/ddr4/ddr4.xci } # read in all other rtl @@ -46,13 +46,6 @@ read_verilog [glob -type f ../../addins/ahbsdc/sdc/*.v] set_property include_dirs {../src/CopiedFiles_do_not_add_to_repo/config ../../config/shared ../../addins/ahbsdc/sdc} [current_fileset] -if {$board=="ArtyA7"} { - add_files -fileset constrs_1 -norecurse ../constraints/constraints-$board.xdc - set_property PROCESSING_ORDER NORMAL [get_files ../constraints/constraints-$board.xdc] -} else { - add_files -fileset constrs_1 -norecurse ../constraints/constraints-$boardSubName.xdc - set_property PROCESSING_ORDER NORMAL [get_files ../constraints/constraints-$boardSubName.xdc] -} # define top level set_property top fpgaTop [current_fileset] @@ -62,6 +55,14 @@ update_compile_order -fileset sources_1 exec mkdir -p reports/ exec rm -rf reports/* +if {$board=="ArtyA7"} { + add_files -fileset constrs_1 -norecurse ../constraints/constraints-$board.xdc + set_property PROCESSING_ORDER NORMAL [get_files ../constraints/constraints-$board.xdc] +} else { + add_files -fileset constrs_1 -norecurse ../constraints/constraints-$boardSubName.xdc + set_property PROCESSING_ORDER NORMAL [get_files ../constraints/constraints-$boardSubName.xdc] +} + report_compile_order -constraints > reports/compile_order.rpt # this is elaboration not synthesis. @@ -89,10 +90,11 @@ report_clock_interaction -file re write_verilog -force -mode funcsim sim/syn-funcsim.v if {$board=="ArtyA7"} { - source ../constraints/small-debug.xdc + #source ../constraints/small-debug.xdc #source ../constraints/small-debug-rvvi.xdc } else { - source ../constraints/vcu-small-debug.xdc + #source ../constraints/vcu-small-debug.xdc + source ../constraints/small-debug.xdc } diff --git a/fpga/generator/xlnx_axi_crossbar.tcl b/fpga/generator/xlnx_axi_crossbar.tcl deleted file mode 100644 index 1d9eb4e78..000000000 --- a/fpga/generator/xlnx_axi_crossbar.tcl +++ /dev/null @@ -1,32 +0,0 @@ -set partNumber $::env(XILINX_PART) -set boardName $::env(XILINX_BOARD) - -# vcu118 board -#set partNumber xcvu9p-flga2104-2L-e -#set boardName xilinx.com:vcu118:part0:2.4 - -# kcu105 board -#set partNumber xcku040-ffva1156-2-e -#set boardName xilinx.com:kcu105:part0:1.7 - -set ipName xlnx_axi_crossbar - -create_project $ipName . -force -part $partNumber -set_property board_part $boardName [current_project] - -create_ip -name axi_crossbar -vendor xilinx.com -library ip -version 2.1 -module_name $ipName - -set_property -dict [list CONFIG.NUM_SI {2} \ - CONFIG.DATA_WIDTH {64} \ - CONFIG.ID_WIDTH {4} \ - CONFIG.M01_S01_READ_CONNECTIVITY {0} \ - CONFIG.M01_S01_WRITE_CONNECTIVITY {0} \ - CONFIG.M00_A00_BASE_ADDR {0x0000000080000000} \ - CONFIG.M01_A00_BASE_ADDR {0x0000000000013000} \ - CONFIG.M00_A00_ADDR_WIDTH {31}] [get_ips $ipName] - -generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] -generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] -create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] -launch_run -jobs 8 ${ipName}_synth_1 -wait_on_run ${ipName}_synth_1 diff --git a/fpga/generator/xlnx_axi_dwidth_conv_32to64.tcl b/fpga/generator/xlnx_axi_dwidth_conv_32to64.tcl deleted file mode 100644 index 97edd97d9..000000000 --- a/fpga/generator/xlnx_axi_dwidth_conv_32to64.tcl +++ /dev/null @@ -1,25 +0,0 @@ -set partNumber $::env(XILINX_PART) -set boardName $::env(XILINX_BOARD) - -# vcu118 board -#set partNumber xcvu9p-flga2104-2L-e -#set boardName xilinx.com:vcu118:part0:2.4 - -# kcu105 board -#set partNumber xcku040-ffva1156-2-e -#set boardName xilinx.com:kcu105:part0:1.7 - -set ipName xlnx_axi_dwidth_conv_32to64 - -create_project $ipName . -force -part $partNumber -set_property board_part $boardName [current_project] - -create_ip -name axi_dwidth_converter -vendor xilinx.com -library ip -version 2.1 -module_name $ipName - -set_property -dict [list CONFIG.Component_Name {axi_dwidth_conv_32to64}] [get_ips $ipName] - -generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] -generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] -create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] -launch_run -jobs 8 ${ipName}_synth_1 -wait_on_run ${ipName}_synth_1 diff --git a/fpga/generator/xlnx_axi_dwidth_conv_64to32.tcl b/fpga/generator/xlnx_axi_dwidth_conv_64to32.tcl deleted file mode 100644 index 3883a8a9d..000000000 --- a/fpga/generator/xlnx_axi_dwidth_conv_64to32.tcl +++ /dev/null @@ -1,27 +0,0 @@ -set partNumber $::env(XILINX_PART) -set boardName $::env(XILINX_BOARD) - -# vcu118 board -#set partNumber xcvu9p-flga2104-2L-e -#set boardName xilinx.com:vcu118:part0:2.4 - -# kcu105 board -#set partNumber xcku040-ffva1156-2-e -#set boardName xilinx.com:kcu105:part0:1.7 - -set ipName xlnx_axi_dwidth_conv_64to32 - -create_project $ipName . -force -part $partNumber -set_property board_part $boardName [current_project] - -create_ip -name axi_dwidth_converter -vendor xilinx.com -library ip -version 2.1 -module_name $ipName - -set_property -dict [list CONFIG.Component_Name {axi_dwidth_conv_64to32} \ - CONFIG.SI_DATA_WIDTH {64} \ - CONFIG.MI_DATA_WIDTH {32}] [get_ips $ipName] - -generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] -generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] -create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] -launch_run -jobs 8 ${ipName}_synth_1 -wait_on_run ${ipName}_synth_1 diff --git a/fpga/generator/xlnx_axi_dwidth_converter.tcl b/fpga/generator/xlnx_axi_dwidth_converter.tcl deleted file mode 100644 index ba979bf01..000000000 --- a/fpga/generator/xlnx_axi_dwidth_converter.tcl +++ /dev/null @@ -1,25 +0,0 @@ -set partNumber $::env(XILINX_PART) -set boardName $::env(XILINX_BOARD) - -# vcu118 board -#set partNumber xcvu9p-flga2104-2L-e -#set boardName xilinx.com:vcu118:part0:2.4 - -# kcu105 board -#set partNumber xcku040-ffva1156-2-e -#set boardName xilinx.com:kcu105:part0:1.7 - -set ipName xlnx_axi_dwidth_converter - -create_project $ipName . -force -part $partNumber -set_property board_part $boardName [current_project] - -create_ip -name axi_dwidth_converter -vendor xilinx.com -library ip -version 2.1 -module_name $ipName - -set_property -dict [list CONFIG.Component_Name {axi_dwidth_converter}] [get_ips $ipName] - -generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] -generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] -create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] -launch_run -jobs 8 ${ipName}_synth_1 -wait_on_run ${ipName}_synth_1 diff --git a/fpga/generator/xlnx_axi_prtcl_conv.tcl b/fpga/generator/xlnx_axi_prtcl_conv.tcl deleted file mode 100644 index 76b6fc6cd..000000000 --- a/fpga/generator/xlnx_axi_prtcl_conv.tcl +++ /dev/null @@ -1,23 +0,0 @@ -set partNumber $::env(XILINX_PART) -set boardName $::env(XILINX_BOARD) - -# vcu118 board -#set partNumber xcvu9p-flga2104-2L-e -#set boardName xilinx.com:vcu118:part0:2.4 - -# kcu105 board -#set partNumber xcku040-ffva1156-2-e -#set boardName xilinx.com:kcu105:part0:1.7 - -set ipName xlnx_axi_prtcl_conv - -create_project $ipName . -force -part $partNumber -set_property board_part $boardName [current_project] - -create_ip -name axi_protocol_converter -vendor xilinx.com -library ip -version 2.1 -module_name $ipName - -generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] -generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] -create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] -launch_run -jobs 8 ${ipName}_synth_1 -wait_on_run ${ipName}_synth_1 diff --git a/fpga/generator/xlnx_ddr4.tcl b/fpga/generator/xlnx_ddr4.tcl index c3aac1f71..2b9d24e70 100644 --- a/fpga/generator/xlnx_ddr4.tcl +++ b/fpga/generator/xlnx_ddr4.tcl @@ -5,7 +5,7 @@ set partNumber xcvu095-ffva2104-2-e set boardName xilinx.com:vcu108:part0:1.2 -set ipName xlnx_ddr4 +set ipName ddr4 create_project $ipName . -force -part $partNumber set_property board_part $boardName [current_project] diff --git a/fpga/src/fpgaTop.sv b/fpga/src/fpgaTop.sv index 20ffd4b08..9ae282966 100644 --- a/fpga/src/fpgaTop.sv +++ b/fpga/src/fpgaTop.sv @@ -34,18 +34,20 @@ module fpgaTop input reset, input south_rst, - input [3:0] GPI, + input [2:0] GPI, output [4:0] GPO, input UARTSin, output UARTSout, - inout [3:0] SDCDat, - output SDCCLK, - inout SDCCmd, - input SDCCD, + // SDC Signals connecting to an SPI peripheral + input SDCIn, + output SDCCLK, + output SDCCmd, + output SDCCS, + input SDCCD, + input SDCWP, - output calib, output cpu_reset, output ahblite_resetn, @@ -65,414 +67,133 @@ module fpgaTop output [0 : 0] c0_ddr4_ck_t ); - wire CPUCLK; - wire c0_ddr4_ui_clk_sync_rst; - wire bus_struct_reset; - wire peripheral_reset; - wire interconnect_aresetn; - wire peripheral_aresetn; - wire mb_reset; - - wire HCLKOpen; - wire HRESETnOpen; - wire [64-1:0] HRDATAEXT; - wire HREADYEXT; - wire HRESPEXT; - (* mark_debug = "true" *) wire HSELEXT; - (* mark_debug = "true" *) wire HSELEXTSDC; // TEMP BOOT SIGNAL - JACOB - wire [55:0] HADDR; - wire [64-1:0] HWDATA; - wire [64/8-1:0] HWSTRB; - wire HWRITE; - wire [2:0] HSIZE; - wire [2:0] HBURST; - wire [1:0] HTRANS; - wire HREADY; - wire [3:0] HPROT; - wire HMASTLOCK; - + logic CPUCLK; + logic c0_ddr4_ui_clk_sync_rst; + logic bus_struct_reset; + logic peripheral_reset; + logic interconnect_aresetn; + logic peripheral_aresetn; + logic mb_reset; + logic HCLKOpen; + logic HRESETnOpen; + logic [64-1:0] HRDATAEXT; + logic HREADYEXT; + logic HRESPEXT; + logic HSELEXT; + logic [55:0] HADDR; + logic [64-1:0] HWDATA; + logic [64/8-1:0] HWSTRB; + logic HWRITE; + logic [2:0] HSIZE; + logic [2:0] HBURST; + logic [1:0] HTRANS; + logic HREADY; + logic [3:0] HPROT; + logic HMASTLOCK; - wire [31:0] GPIOIN, GPIOOUT, GPIOEN; + logic RVVIStall; - // Old SDC connections - // wire SDCCmdIn; - // wire SDCCmdOE; - // wire SDCCmdOut; + logic [31:0] GPIOIN, GPIOOUT, GPIOEN; - (* mark_debug = "true" *)wire [3:0] m_axi_awid; - (* mark_debug = "true" *)wire [7:0] m_axi_awlen; - (* mark_debug = "true" *)wire [2:0] m_axi_awsize; - (* mark_debug = "true" *)wire [1:0] m_axi_awburst; - (* mark_debug = "true" *)wire [3:0] m_axi_awcache; - (* mark_debug = "true" *)wire [31:0] m_axi_awaddr; - (* mark_debug = "true" *)wire [2:0] m_axi_awprot; - (* mark_debug = "true" *)wire m_axi_awvalid; - (* mark_debug = "true" *)wire m_axi_awready; - (* mark_debug = "true" *)wire m_axi_awlock; - (* mark_debug = "true" *)wire [63:0] m_axi_wdata; - (* mark_debug = "true" *)wire [7:0] m_axi_wstrb; - (* mark_debug = "true" *)wire m_axi_wlast; - (* mark_debug = "true" *)wire m_axi_wvalid; - (* mark_debug = "true" *)wire m_axi_wready; - (* mark_debug = "true" *)wire [3:0] m_axi_bid; - (* mark_debug = "true" *)wire [1:0] m_axi_bresp; - (* mark_debug = "true" *)wire m_axi_bvalid; - (* mark_debug = "true" *)wire m_axi_bready; - (* mark_debug = "true" *)wire [3:0] m_axi_arid; - (* mark_debug = "true" *)wire [7:0] m_axi_arlen; - (* mark_debug = "true" *)wire [2:0] m_axi_arsize; - (* mark_debug = "true" *)wire [1:0] m_axi_arburst; - (* mark_debug = "true" *)wire [2:0] m_axi_arprot; - (* mark_debug = "true" *)wire [3:0] m_axi_arcache; - (* mark_debug = "true" *)wire m_axi_arvalid; - (* mark_debug = "true" *)wire [31:0] m_axi_araddr; - (* mark_debug = "true" *)wire m_axi_arlock; - (* mark_debug = "true" *)wire m_axi_arready; - (* mark_debug = "true" *)wire [3:0] m_axi_rid; - (* mark_debug = "true" *)wire [63:0] m_axi_rdata; - (* mark_debug = "true" *)wire [1:0] m_axi_rresp; - (* mark_debug = "true" *)wire m_axi_rvalid; - (* mark_debug = "true" *)wire m_axi_rlast; - (* mark_debug = "true" *)wire m_axi_rready; + logic [3:0] m_axi_awid; + logic [7:0] m_axi_awlen; + logic [2:0] m_axi_awsize; + logic [1:0] m_axi_awburst; + logic [3:0] m_axi_awcache; + logic [31:0] m_axi_awaddr; + logic [2:0] m_axi_awprot; + logic m_axi_awvalid; + logic m_axi_awready; + logic m_axi_awlock; + logic [63:0] m_axi_wdata; + logic [7:0] m_axi_wstrb; + logic m_axi_wlast; + logic m_axi_wvalid; + logic m_axi_wready; + logic [3:0] m_axi_bid; + logic [1:0] m_axi_bresp; + logic m_axi_bvalid; + logic m_axi_bready; + logic [3:0] m_axi_arid; + logic [7:0] m_axi_arlen; + logic [2:0] m_axi_arsize; + logic [1:0] m_axi_arburst; + logic [2:0] m_axi_arprot; + logic [3:0] m_axi_arcache; + logic m_axi_arvalid; + logic [31:0] m_axi_araddr; + logic m_axi_arlock; + logic m_axi_arready; + logic [3:0] m_axi_rid; + logic [63:0] m_axi_rdata; + logic [1:0] m_axi_rresp; + logic m_axi_rvalid; + logic m_axi_rlast; + logic m_axi_rready; // Extra Bus signals - wire [3:0] BUS_axi_arregion; - wire [3:0] BUS_axi_arqos; - wire [3:0] BUS_axi_awregion; - wire [3:0] BUS_axi_awqos; + logic [3:0] BUS_axi_arregion; + logic [3:0] BUS_axi_arqos; + logic [3:0] BUS_axi_awregion; + logic [3:0] BUS_axi_awqos; // Bus signals - wire [3:0] BUS_axi_awid; - wire [7:0] BUS_axi_awlen; - wire [2:0] BUS_axi_awsize; - wire [1:0] BUS_axi_awburst; - wire [3:0] BUS_axi_awcache; - wire [30:0] BUS_axi_awaddr; - wire [2:0] BUS_axi_awprot; - wire BUS_axi_awvalid; - wire BUS_axi_awready; - wire BUS_axi_awlock; - wire [63:0] BUS_axi_wdata; - wire [7:0] BUS_axi_wstrb; - wire BUS_axi_wlast; - wire BUS_axi_wvalid; - wire BUS_axi_wready; - wire [3:0] BUS_axi_bid; - wire [1:0] BUS_axi_bresp; - wire BUS_axi_bvalid; - wire BUS_axi_bready; - wire [3:0] BUS_axi_arid; - wire [7:0] BUS_axi_arlen; - wire [2:0] BUS_axi_arsize; - wire [1:0] BUS_axi_arburst; - wire [2:0] BUS_axi_arprot; - wire [3:0] BUS_axi_arcache; - wire BUS_axi_arvalid; - wire [30:0] BUS_axi_araddr; - wire BUS_axi_arlock; - wire BUS_axi_arready; - wire [3:0] BUS_axi_rid; - wire [63:0] BUS_axi_rdata; - wire [1:0] BUS_axi_rresp; - wire BUS_axi_rvalid; - wire BUS_axi_rlast; - wire BUS_axi_rready; + logic [3:0] BUS_axi_awid; + logic [7:0] BUS_axi_awlen; + logic [2:0] BUS_axi_awsize; + logic [1:0] BUS_axi_awburst; + logic [3:0] BUS_axi_awcache; + logic [30:0] BUS_axi_awaddr; + logic [2:0] BUS_axi_awprot; + logic BUS_axi_awvalid; + logic BUS_axi_awready; + logic BUS_axi_awlock; + logic [63:0] BUS_axi_wdata; + logic [7:0] BUS_axi_wstrb; + logic BUS_axi_wlast; + logic BUS_axi_wvalid; + logic BUS_axi_wready; + logic [3:0] BUS_axi_bid; + logic [1:0] BUS_axi_bresp; + logic BUS_axi_bvalid; + logic BUS_axi_bready; + logic [3:0] BUS_axi_arid; + logic [7:0] BUS_axi_arlen; + logic [2:0] BUS_axi_arsize; + logic [1:0] BUS_axi_arburst; + logic [2:0] BUS_axi_arprot; + logic [3:0] BUS_axi_arcache; + logic BUS_axi_arvalid; + logic [30:0] BUS_axi_araddr; + logic BUS_axi_arlock; + logic BUS_axi_arready; + logic [3:0] BUS_axi_rid; + logic [63:0] BUS_axi_rdata; + logic [1:0] BUS_axi_rresp; + logic BUS_axi_rvalid; + logic BUS_axi_rlast; + logic BUS_axi_rready; - wire BUSCLK; - + logic BUSCLK; - wire c0_init_calib_complete; - wire dbg_clk; - wire [511 : 0] dbg_bus; + logic c0_init_calib_complete; + logic dbg_clk; + logic [511 : 0] dbg_bus; - wire CLK208; + logic CLK208; - - // Crossbar to Bus ------------------------------------------------ - - (* mark_debug = "true" *)wire s00_axi_aclk; - (* mark_debug = "true" *)wire s00_axi_aresetn; - (* mark_debug = "true" *)wire [3:0] s00_axi_awid; - (* mark_debug = "true" *)wire [31:0]s00_axi_awaddr; - (* mark_debug = "true" *)wire [7:0]s00_axi_awlen; - (* mark_debug = "true" *)wire [2:0]s00_axi_awsize; - (* mark_debug = "true" *)wire [1:0]s00_axi_awburst; - (* mark_debug = "true" *)wire [0:0]s00_axi_awlock; - (* mark_debug = "true" *)wire [3:0]s00_axi_awcache; - (* mark_debug = "true" *)wire [2:0]s00_axi_awprot; - (* mark_debug = "true" *)wire [3:0]s00_axi_awregion; - (* mark_debug = "true" *)wire [3:0]s00_axi_awqos; - (* mark_debug = "true" *) wire s00_axi_awvalid; - (* mark_debug = "true" *) wire s00_axi_awready; - (* mark_debug = "true" *)wire [63:0]s00_axi_wdata; - (* mark_debug = "true" *)wire [7:0]s00_axi_wstrb; - (* mark_debug = "true" *)wire s00_axi_wlast; - (* mark_debug = "true" *)wire s00_axi_wvalid; - (* mark_debug = "true" *)wire s00_axi_wready; - (* mark_debug = "true" *)wire [1:0]s00_axi_bresp; - (* mark_debug = "true" *)wire s00_axi_bvalid; - (* mark_debug = "true" *)wire s00_axi_bready; - (* mark_debug = "true" *)wire [31:0]s00_axi_araddr; - (* mark_debug = "true" *)wire [7:0]s00_axi_arlen; - (* mark_debug = "true" *)wire [2:0]s00_axi_arsize; - (* mark_debug = "true" *)wire [1:0]s00_axi_arburst; - (* mark_debug = "true" *)wire [0:0]s00_axi_arlock; - (* mark_debug = "true" *)wire [3:0]s00_axi_arcache; - (* mark_debug = "true" *)wire [2:0]s00_axi_arprot; - (* mark_debug = "true" *)wire [3:0]s00_axi_arregion; - (* mark_debug = "true" *)wire [3:0]s00_axi_arqos; - (* mark_debug = "true" *)wire s00_axi_arvalid; - (* mark_debug = "true" *)wire s00_axi_arready; - (* mark_debug = "true" *)wire [63:0]s00_axi_rdata; - (* mark_debug = "true" *)wire [1:0]s00_axi_rresp; - (* mark_debug = "true" *)wire s00_axi_rlast; - (* mark_debug = "true" *)wire s00_axi_rvalid; - (* mark_debug = "true" *)wire s00_axi_rready; - - (* mark_debug = "true" *)wire [3:0] s00_axi_bid; - (* mark_debug = "true" *)wire [3:0] s00_axi_rid; - - // 64to32 dwidth converter input interface------------------------- - wire s01_axi_aclk; - wire s01_axi_aresetn; - wire [3:0]s01_axi_awid; - wire [31:0]s01_axi_awaddr; - wire [7:0]s01_axi_awlen; - wire [2:0]s01_axi_awsize; - wire [1:0]s01_axi_awburst; - wire [0:0]s01_axi_awlock; - wire [3:0]s01_axi_awcache; - wire [2:0]s01_axi_awprot; - wire [3:0]s01_axi_awregion; - wire [3:0]s01_axi_awqos; // qos signals need to be 0 for SDC - (* mark_debug = "true" *) wire s01_axi_awvalid; - (* mark_debug = "true" *) wire s01_axi_awready; - wire [63:0]s01_axi_wdata; - wire [7:0]s01_axi_wstrb; - wire s01_axi_wlast; - wire s01_axi_wvalid; - wire s01_axi_wready; - wire [1:0]s01_axi_bresp; - wire s01_axi_bvalid; - wire s01_axi_bready; - wire [31:0]s01_axi_araddr; - wire [7:0]s01_axi_arlen; - wire [2:0]s01_axi_arsize; - wire [1:0]s01_axi_arburst; - wire [0:0]s01_axi_arlock; - wire [3:0]s01_axi_arcache; - wire [2:0]s01_axi_arprot; - wire [3:0]s01_axi_arregion; - wire [3:0]s01_axi_arqos; // - wire s01_axi_arvalid; - wire s01_axi_arready; - wire [63:0]s01_axi_rdata; - wire [1:0]s01_axi_rresp; - wire s01_axi_rlast; - wire s01_axi_rvalid; - wire s01_axi_rready; - - // Output Interface - wire [31:0]axi4in_axi_awaddr; - wire [7:0]axi4in_axi_awlen; - wire [2:0]axi4in_axi_awsize; - wire [1:0]axi4in_axi_awburst; - wire [0:0]axi4in_axi_awlock; - wire [3:0]axi4in_axi_awcache; - wire [2:0]axi4in_axi_awprot; - wire [3:0]axi4in_axi_awregion; - wire [3:0]axi4in_axi_awqos; - (* mark_debug = "true" *) wire axi4in_axi_awvalid; - (* mark_debug = "true" *) wire axi4in_axi_awready; - wire [31:0]axi4in_axi_wdata; - wire [3:0]axi4in_axi_wstrb; - wire axi4in_axi_wlast; - wire axi4in_axi_wvalid; - wire axi4in_axi_wready; - wire [1:0]axi4in_axi_bresp; - wire axi4in_axi_bvalid; - wire axi4in_axi_bready; - wire [31:0]axi4in_axi_araddr; - wire [7:0]axi4in_axi_arlen; - wire [2:0]axi4in_axi_arsize; - wire [1:0]axi4in_axi_arburst; - wire [0:0]axi4in_axi_arlock; - wire [3:0]axi4in_axi_arcache; - wire [2:0]axi4in_axi_arprot; - wire [3:0]axi4in_axi_arregion; - wire [3:0]axi4in_axi_arqos; - wire axi4in_axi_arvalid; - wire axi4in_axi_arready; - wire [31:0]axi4in_axi_rdata; - wire [1:0]axi4in_axi_rresp; - wire axi4in_axi_rlast; - wire axi4in_axi_rvalid; - wire axi4in_axi_rready; - - // AXI4 to AXI4-Lite Protocol converter output - (* mark_debug = "true" *) wire [31:0]SDCin_axi_awaddr; - (* mark_debug = "true" *) wire [2:0]SDCin_axi_awprot; - (* mark_debug = "true" *) wire SDCin_axi_awvalid; - (* mark_debug = "true" *) wire SDCin_axi_awready; - (* mark_debug = "true" *) wire [31:0]SDCin_axi_wdata; - (* mark_debug = "true" *) wire [3:0]SDCin_axi_wstrb; - (* mark_debug = "true" *) wire SDCin_axi_wvalid; - (* mark_debug = "true" *) wire SDCin_axi_wready; - (* mark_debug = "true" *) wire [1:0]SDCin_axi_bresp; - (* mark_debug = "true" *) wire SDCin_axi_bvalid; - (* mark_debug = "true" *) wire SDCin_axi_bready; - (* mark_debug = "true" *) wire [31:0]SDCin_axi_araddr; - (* mark_debug = "true" *) wire [2:0]SDCin_axi_arprot; - (* mark_debug = "true" *) wire SDCin_axi_arvalid; - (* mark_debug = "true" *) wire SDCin_axi_arready; - (* mark_debug = "true" *) wire [31:0]SDCin_axi_rdata; - (* mark_debug = "true" *) wire [1:0]SDCin_axi_rresp; - (* mark_debug = "true" *) wire SDCin_axi_rvalid; - (* mark_debug = "true" *) wire SDCin_axi_rready; - // ---------------------------------------------------------------- - - // 32to64 dwidth converter input interface ----------------------- - (* mark_debug = "true" *) wire [31:0]SDCout_axi_awaddr; - (* mark_debug = "true" *) wire [7:0]SDCout_axi_awlen; - wire [2:0]SDCout_axi_awsize; - wire [1:0]SDCout_axi_awburst; - wire [0:0]SDCout_axi_awlock; - wire [3:0]SDCout_axi_awcache; - wire [2:0]SDCout_axi_awprot; - wire [3:0]SDCout_axi_awregion; - wire [3:0]SDCout_axi_awqos; - (* mark_debug = "true" *) wire SDCout_axi_awvalid; - (* mark_debug = "true" *) wire SDCout_axi_awready; - (* mark_debug = "true" *) wire [31:0]SDCout_axi_wdata; - wire [3:0]SDCout_axi_wstrb; - (* mark_debug = "true" *) wire SDCout_axi_wlast; - (* mark_debug = "true" *) wire SDCout_axi_wvalid; - (* mark_debug = "true" *)wire SDCout_axi_wready; - (* mark_debug = "true" *) wire [1:0]SDCout_axi_bresp; - (* mark_debug = "true" *) wire SDCout_axi_bvalid; - (* mark_debug = "true" *) wire SDCout_axi_bready; - wire [31:0]SDCout_axi_araddr; - wire [7:0]SDCout_axi_arlen; - wire [2:0]SDCout_axi_arsize; - wire [1:0]SDCout_axi_arburst; - wire [0:0]SDCout_axi_arlock; - wire [3:0]SDCout_axi_arcache; - wire [2:0]SDCout_axi_arprot; - wire [3:0]SDCout_axi_arregion; - wire [3:0]SDCout_axi_arqos; - wire SDCout_axi_arvalid; - wire SDCout_axi_arready; - wire [31:0]SDCout_axi_rdata; - wire [1:0]SDCout_axi_rresp; - wire SDCout_axi_rlast; - wire SDCout_axi_rvalid; - wire SDCout_axi_rready; - - // Output Interface - (* mark_debug = "true" *) wire [3:0]m01_axi_awid; - (* mark_debug = "true" *) wire [31:0]m01_axi_awaddr; - (* mark_debug = "true" *) wire [7:0]m01_axi_awlen; - (* mark_debug = "true" *) wire [2:0]m01_axi_awsize; - (* mark_debug = "true" *) wire [1:0]m01_axi_awburst; - (* mark_debug = "true" *) wire [0:0]m01_axi_awlock; - (* mark_debug = "true" *) wire [3:0]m01_axi_awcache; - (* mark_debug = "true" *) wire [2:0]m01_axi_awprot; - (* mark_debug = "true" *) wire [3:0]m01_axi_awregion; - (* mark_debug = "true" *) wire [3:0]m01_axi_awqos; - (* mark_debug = "true" *) wire m01_axi_awvalid; - (* mark_debug = "true" *) wire m01_axi_awready; - (* mark_debug = "true" *) wire [63:0]m01_axi_wdata; - (* mark_debug = "true" *) wire [7:0]m01_axi_wstrb; - (* mark_debug = "true" *) wire m01_axi_wlast; - (* mark_debug = "true" *) wire m01_axi_wvalid; - (* mark_debug = "true" *) wire m01_axi_wready; - (* mark_debug = "true" *) wire [3:0] m01_axi_bid; - (* mark_debug = "true" *) wire [1:0]m01_axi_bresp; - (* mark_debug = "true" *) wire m01_axi_bvalid; - (* mark_debug = "true" *) wire m01_axi_bready; - (* mark_debug = "true" *) wire [3:0] m01_axi_arid; - (* mark_debug = "true" *) wire [31:0]m01_axi_araddr; - (* mark_debug = "true" *) wire [7:0]m01_axi_arlen; - (* mark_debug = "true" *) wire [2:0]m01_axi_arsize; - (* mark_debug = "true" *) wire [1:0]m01_axi_arburst; - (* mark_debug = "true" *) wire [0:0]m01_axi_arlock; - (* mark_debug = "true" *) wire [3:0]m01_axi_arcache; - (* mark_debug = "true" *) wire [2:0]m01_axi_arprot; - (* mark_debug = "true" *) wire [3:0]m01_axi_arregion; - (* mark_debug = "true" *) wire [3:0]m01_axi_arqos; - (* mark_debug = "true" *) wire m01_axi_arvalid; - (* mark_debug = "true" *) wire m01_axi_arready; - (* mark_debug = "true" *) wire [3:0] m01_axi_rid; - (* mark_debug = "true" *) wire [63:0]m01_axi_rdata; - (* mark_debug = "true" *) wire [1:0]m01_axi_rresp; - (* mark_debug = "true" *) wire m01_axi_rlast; - (* mark_debug = "true" *) wire m01_axi_rvalid; - (* mark_debug = "true" *) wire m01_axi_rready; - - // Old SDC input - // wire [3:0] SDCDatIn; - - // New SDC Command IOBUF connections - wire sd_cmd_i; - wire sd_cmd_reg_o; - wire sd_cmd_reg_t; - - // SD Card Interrupt signal - (* mark_debug = "true" *) wire SDCIntr; - - // New SDC Data IOBUF connections - wire [3:0] sd_dat_i; - wire [3:0] sd_dat_reg_o; - wire sd_dat_reg_t; - - assign GPIOIN = {28'b0, GPI}; + assign GPIOIN = {25'b0, SDCCD, SDCWP, 2'b0, GPI}; assign GPO = GPIOOUT[4:0]; assign ahblite_resetn = peripheral_aresetn; assign cpu_reset = bus_struct_reset; - assign calib = c0_init_calib_complete; + logic [3:0] SDCCSin; + assign SDCCS = SDCCSin[0]; - // SD Card Tristate - /* - IOBUF iobufSDCMD(.T(~SDCCmdOE), // iobuf's T is active low - .I(SDCCmdOut), - .O(SDCCmdIn), - .IO(SDCCmd)); - - genvar i; - generate - for (i = 0; i < 4; i = i + 1) begin - IOBUF iobufSDCDat(.T(1'b1), - .I(1'b0), - .O(SDCDatIn[i]), - .IO(SDCDat[i])); - end - endgenerate - */ - - // IOBUFS for new SDC peripheral - IOBUF IOBUF_cmd (.O(sd_cmd_i), .IO(SDCCmd), .I(sd_cmd_reg_o), .T(sd_cmd_reg_t)); - genvar i; - generate - for (i = 0; i < 4; i = i + 1) begin - IOBUF iobufSDCDat(.T(sd_dat_reg_t), - .I(sd_dat_reg_o[i]), - .O(sd_dat_i[i]), - .IO(SDCDat[i]) ); - end - endgenerate - - // IOBUF IOBUF_dat0 (.O(sd_dat_i[0]), .IO(sdio_dat[0]), .I(sd_dat_reg_o[0]), .T(sd_dat_reg_t)); - // IOBUF IOBUF_dat1 (.O(sd_dat_i[1]), .IO(sdio_dat[1]), .I(sd_dat_reg_o[1]), .T(sd_dat_reg_t)); - // IOBUF IOBUF_dat2 (.O(sd_dat_i[2]), .IO(sdio_dat[2]), .I(sd_dat_reg_o[2]), .T(sd_dat_reg_t)); - // IOBUF IOBUF_dat3 (.O(sd_dat_i[3]), .IO(sdio_dat[3]), .I(sd_dat_reg_o[3]), .T(sd_dat_reg_t)); - - - // reset controller XILINX IP - xlnx_proc_sys_reset xlnx_proc_sys_reset_0 + sysrst sysrst (.slowest_sync_clk(CPUCLK), .ext_reset_in(c0_ddr4_ui_clk_sync_rst), .aux_reset_in(south_rst), @@ -486,58 +207,21 @@ module fpgaTop `include "parameter-defs.vh" + // Wally wallypipelinedsoc #(P) wallypipelinedsoc(.clk(CPUCLK), .reset_ext(bus_struct_reset), .reset(), .HRDATAEXT, .HREADYEXT, .HRESPEXT, .HSELEXT, - .HSELEXTSDC, .HCLK(HCLKOpen), .HRESETn(HRESETnOpen), + .HCLK(HCLKOpen), .HRESETn(HRESETnOpen), .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0), .GPIOIN, .GPIOOUT, .GPIOEN, - .UARTSin, .UARTSout, .SDCIntr); - - - // RT and JP: FIXME add sdc interrupt and HSELEXTSDC, remove old sdc after the new sdc ahb version is implemented - // wallypipelinedsocwrapper wallypipelinedsocwrapper - // (.clk(CPUCLK), - // .reset_ext(bus_struct_reset), - // // bus interface - // .HRDATAEXT(HRDATAEXT), - // .HREADYEXT(HREADYEXT), - // .HRESPEXT(HRESPEXT), - // .HSELEXT(HSELEXT), - // .HSELEXTSDC(HSELEXTSDC), - // .HCLK(HCLKOpen), // open - // .HRESETn(HRESETnOpen), // open - // .HADDR(HADDR), - // .HWDATA(HWDATA), - // .HWRITE(HWRITE), - // .HSIZE(HSIZE), - // .HBURST(HBURST), - // .HPROT(HPROT), - // .HTRANS(HTRANS), - // .HMASTLOCK(HMASTLOCK), - // .HREADY(HREADY), - // // GPIO - // .GPIOIN(GPIOIN), - // .GPIOOUT(GPIOOUT), - // .GPIOEN(GPIOEN), - // // UART - // .UARTSin(UARTSin), - // .UARTSout(UARTSout), - // .SDCIntr(SDCIntr) - // // SD Card - // /*.SDCDatIn(SDCDatIn), - // .SDCCmdIn(SDCCmdIn), - // .SDCCmdOut(SDCCmdOut), - // .SDCCmdOE(SDCCmdOE), - // .SDCCLK(SDCCLK));*/ - // ); + .UARTSin, .UARTSout, .SDCIn, .SDCCmd, .SDCCS(SDCCSin), .SDCCLK, .ExternalStall(RVVIStall)); // ahb lite to axi bridge - xlnx_ahblite_axi_bridge xlnx_ahblite_axi_bridge_0 + ahbaxibridge ahbaxibridge (.s_ahb_hclk(CPUCLK), .s_ahb_hresetn(peripheral_aresetn), - .s_ahb_hsel(HSELEXT | HSELEXTSDC), + .s_ahb_hsel(HSELEXT), .s_ahb_haddr(HADDR), .s_ahb_hprot(HPROT), .s_ahb_htrans(HTRANS), @@ -585,431 +269,48 @@ module fpgaTop .m_axi_rlast(m_axi_rlast), .m_axi_rready(m_axi_rready)); - // AXI Crossbar for arbitrating the SDC and CPU -------------- - xlnx_axi_crossbar xlnx_axi_crossbar_0 - (.aclk(CPUCLK), - .aresetn(peripheral_aresetn), - - // Connect Masters - .s_axi_awid({4'b1000, m_axi_awid}), - .s_axi_awaddr({m01_axi_awaddr, m_axi_awaddr}), - .s_axi_awlen({m01_axi_awlen, m_axi_awlen}), - .s_axi_awsize({m01_axi_awsize, m_axi_awsize}), - .s_axi_awburst({m01_axi_awburst, m_axi_awburst}), - .s_axi_awlock({m01_axi_awlock, m_axi_awlock}), - .s_axi_awcache({m01_axi_awcache, m_axi_awcache}), - .s_axi_awprot({m01_axi_awprot, m_axi_awprot}), - .s_axi_awqos(8'b0), - .s_axi_awvalid({m01_axi_awvalid, m_axi_awvalid}), - .s_axi_awready({m01_axi_awready, m_axi_awready}), - .s_axi_wdata({m01_axi_wdata, m_axi_wdata}), - .s_axi_wstrb({m01_axi_wstrb, m_axi_wstrb}), - .s_axi_wlast({m01_axi_wlast, m_axi_wlast}), - .s_axi_wvalid({m01_axi_wvalid, m_axi_wvalid}), - .s_axi_wready({m01_axi_wready, m_axi_wready}), - .s_axi_bid({m01_axi_bid, m_axi_bid}), - .s_axi_bresp({m01_axi_bresp, m_axi_bresp}), - .s_axi_bvalid({m01_axi_bvalid, m_axi_bvalid}), - .s_axi_bready({m01_axi_bready, m_axi_bready}), - .s_axi_arid({4'b1000, m_axi_arid}), - .s_axi_araddr({m01_axi_araddr, m_axi_araddr}), - .s_axi_arlen({m01_axi_arlen, m_axi_arlen}), - .s_axi_arsize({m01_axi_arsize, m_axi_arsize}), - .s_axi_arburst({m01_axi_arburst, m_axi_arburst}), - .s_axi_arlock({m01_axi_arlock, m_axi_arlock}), - .s_axi_arcache({m01_axi_arcache, m_axi_arcache}), - .s_axi_arprot({m01_axi_arprot, m_axi_arprot}), - .s_axi_arqos(8'b0), - .s_axi_arvalid({m01_axi_arvalid, m_axi_arvalid}), - .s_axi_arready({m01_axi_arready, m_axi_arready}), - .s_axi_rid({m01_axi_rid, m_axi_rid}), - .s_axi_rdata({m01_axi_rdata, m_axi_rdata}), - .s_axi_rresp({m01_axi_rresp, m_axi_rresp}), - .s_axi_rlast({m01_axi_rlast, m_axi_rlast}), - .s_axi_rvalid({m01_axi_rvalid, m_axi_rvalid}), - .s_axi_rready({m01_axi_rready, m_axi_rready}), - - // Connect Slaves - .m_axi_awid({s01_axi_awid, s00_axi_awid}), - .m_axi_awlen({s01_axi_awlen, s00_axi_awlen}), - .m_axi_awsize({s01_axi_awsize, s00_axi_awsize}), - .m_axi_awburst({s01_axi_awburst, s00_axi_awburst}), - .m_axi_awcache({s01_axi_awcache, s00_axi_awcache}), - .m_axi_awaddr({s01_axi_awaddr, s00_axi_awaddr}), - .m_axi_awprot({s01_axi_awprot, s00_axi_awprot}), - .m_axi_awregion({s01_axi_awregion, s00_axi_awregion}), - .m_axi_awqos({s01_axi_awqos, s00_axi_awqos}), - .m_axi_awvalid({s01_axi_awvalid, s00_axi_awvalid}), - .m_axi_awready({s01_axi_awready, s00_axi_awready}), - .m_axi_awlock({s01_axi_awlock, s00_axi_awlock}), - .m_axi_wdata({s01_axi_wdata, s00_axi_wdata}), - .m_axi_wstrb({s01_axi_wstrb, s00_axi_wstrb}), - .m_axi_wlast({s01_axi_wlast, s00_axi_wlast}), - .m_axi_wvalid({s01_axi_wvalid, s00_axi_wvalid}), - .m_axi_wready({s01_axi_wready, s00_axi_wready}), - .m_axi_bid({4'b1000, s00_axi_bid}), - .m_axi_bresp({s01_axi_bresp, s00_axi_bresp}), - .m_axi_bvalid({s01_axi_bvalid, s00_axi_bvalid}), - .m_axi_bready({s01_axi_bready, s00_axi_bready}), - .m_axi_arid({s01_axi_arid, s00_axi_arid}), - .m_axi_arlen({s01_axi_arlen, s00_axi_arlen}), - .m_axi_arsize({s01_axi_arsize, s00_axi_arsize}), - .m_axi_arburst({s01_axi_arburst, s00_axi_arburst}), - .m_axi_arprot({s01_axi_arprot, s00_axi_arprot}), - .m_axi_arregion({s01_axi_arregion, s00_axi_arregion}), - .m_axi_arqos({s01_axi_arqos, s00_axi_arqos}), - .m_axi_arcache({s01_axi_arcache, s00_axi_arcache}), - .m_axi_arvalid({s01_axi_arvalid, s00_axi_arvalid}), - .m_axi_araddr({s01_axi_araddr, s00_axi_araddr}), - .m_axi_arlock({s01_axi_arlock, s00_axi_arlock}), - .m_axi_arready({s01_axi_arready, s00_axi_arready}), - .m_axi_rid({4'b1000, s00_axi_rid}), - .m_axi_rdata({s01_axi_rdata, s00_axi_rdata}), - .m_axi_rresp({s01_axi_rresp, s00_axi_rresp}), - .m_axi_rvalid({s01_axi_rvalid, s00_axi_rvalid}), - .m_axi_rlast({s01_axi_rlast, s00_axi_rlast}), - .m_axi_rready({s01_axi_rready, s00_axi_rready}) - ); - - // ----------------------------------------------------- - - // SDC Implementation ---------------------------------- - // - // The SDC peripheral from Eugene Tarassov takes in an AXI4Lite - // interface and outputs an AXI4 interface. In order to convert from - // one to the other, we use these dwidth converters to make sure the - // bit widths match the rest of the bus. - - xlnx_axi_dwidth_conv_64to32 axi_conv_down - (.s_axi_aclk(CPUCLK), - .s_axi_aresetn(peripheral_aresetn), - - // Slave interface - .s_axi_awaddr(s01_axi_awaddr), - .s_axi_awlen(s01_axi_awlen), - .s_axi_awsize(s01_axi_awsize), - .s_axi_awburst(s01_axi_awburst), - .s_axi_awlock(s01_axi_awlock), - .s_axi_awcache(s01_axi_awcache), - .s_axi_awprot(s01_axi_awprot), - .s_axi_awregion(s01_axi_awregion), - .s_axi_awqos(4'b0), - .s_axi_awvalid(s01_axi_awvalid), - .s_axi_awready(s01_axi_awready), - .s_axi_wdata(s01_axi_wdata), - .s_axi_wstrb(s01_axi_wstrb), - .s_axi_wlast(s01_axi_wlast), - .s_axi_wvalid(s01_axi_wvalid), - .s_axi_wready(s01_axi_wready), - .s_axi_bresp(s01_axi_bresp), - .s_axi_bvalid(s01_axi_bvalid), - .s_axi_bready(s01_axi_bready), - .s_axi_araddr(s01_axi_araddr), - .s_axi_arlen(s01_axi_arlen), - .s_axi_arsize(s01_axi_arsize), - .s_axi_arburst(s01_axi_arburst), - .s_axi_arlock(s01_axi_arlock), - .s_axi_arcache(s01_axi_arcache), - .s_axi_arprot(s01_axi_arprot), - .s_axi_arregion(s01_axi_arregion), - .s_axi_arqos(4'b0), - .s_axi_arvalid(s01_axi_arvalid), - .s_axi_arready(s01_axi_arready), - .s_axi_rdata(s01_axi_rdata), - .s_axi_rresp(s01_axi_rresp), - .s_axi_rlast(s01_axi_rlast), - .s_axi_rvalid(s01_axi_rvalid), - .s_axi_rready(s01_axi_rready), - - // Master interface - .m_axi_awaddr(axi4in_axi_awaddr), - .m_axi_awlen(axi4in_axi_awlen), - .m_axi_awsize(axi4in_axi_awsize), - .m_axi_awburst(axi4in_axi_awburst), - .m_axi_awlock(axi4in_axi_awlock), - .m_axi_awcache(axi4in_axi_awcache), - .m_axi_awprot(axi4in_axi_awprot), - .m_axi_awregion(axi4in_axi_awregion), - .m_axi_awqos(axi4in_axi_awqos), - .m_axi_awvalid(axi4in_axi_awvalid), - .m_axi_awready(axi4in_axi_awready), - .m_axi_wdata(axi4in_axi_wdata), - .m_axi_wstrb(axi4in_axi_wstrb), - .m_axi_wlast(axi4in_axi_wlast), - .m_axi_wvalid(axi4in_axi_wvalid), - .m_axi_wready(axi4in_axi_wready), - .m_axi_bresp(axi4in_axi_bresp), - .m_axi_bvalid(axi4in_axi_bvalid), - .m_axi_bready(axi4in_axi_bready), - .m_axi_araddr(axi4in_axi_araddr), - .m_axi_arlen(axi4in_axi_arlen), - .m_axi_arsize(axi4in_axi_arsize), - .m_axi_arburst(axi4in_axi_arburst), - .m_axi_arlock(axi4in_axi_arlock), - .m_axi_arcache(axi4in_axi_arcache), - .m_axi_arprot(axi4in_axi_arprot), - .m_axi_arregion(axi4in_axi_arregion), - .m_axi_arqos(axi4in_axi_arqos), - .m_axi_arvalid(axi4in_axi_arvalid), - .m_axi_arready(axi4in_axi_arready), - .m_axi_rdata(axi4in_axi_rdata), - .m_axi_rresp(axi4in_axi_rresp), - .m_axi_rlast(axi4in_axi_rlast), - .m_axi_rvalid(axi4in_axi_rvalid), - .m_axi_rready(axi4in_axi_rready) - ); - - xlnx_axi_prtcl_conv axi4tolite - (.aclk(CPUCLK), - .aresetn(peripheral_aresetn), - - // AXI4 In - .s_axi_awaddr(axi4in_axi_awaddr), - .s_axi_awlen(axi4in_axi_awlen), - .s_axi_awsize(axi4in_axi_awsize), - .s_axi_awburst(axi4in_axi_awburst), - .s_axi_awlock(axi4in_axi_awlock), - .s_axi_awcache(axi4in_axi_awcache), - .s_axi_awprot(axi4in_axi_awprot), - .s_axi_awregion(axi4in_axi_awregion), - .s_axi_awqos(axi4in_axi_awqos), - .s_axi_awvalid(axi4in_axi_awvalid), - .s_axi_awready(axi4in_axi_awready), - .s_axi_wdata(axi4in_axi_wdata), - .s_axi_wstrb(axi4in_axi_wstrb), - .s_axi_wlast(axi4in_axi_wlast), - .s_axi_wvalid(axi4in_axi_wvalid), - .s_axi_wready(axi4in_axi_wready), - .s_axi_bresp(axi4in_axi_bresp), - .s_axi_bvalid(axi4in_axi_bvalid), - .s_axi_bready(axi4in_axi_bready), - .s_axi_araddr(axi4in_axi_araddr), - .s_axi_arlen(axi4in_axi_arlen), - .s_axi_arsize(axi4in_axi_arsize), - .s_axi_arburst(axi4in_axi_arburst), - .s_axi_arlock(axi4in_axi_arlock), - .s_axi_arcache(axi4in_axi_arcache), - .s_axi_arprot(axi4in_axi_arprot), - .s_axi_arregion(axi4in_axi_arregion), - .s_axi_arqos(axi4in_axi_arqos), - .s_axi_arvalid(axi4in_axi_arvalid), - .s_axi_arready(axi4in_axi_arready), - .s_axi_rdata(axi4in_axi_rdata), - .s_axi_rresp(axi4in_axi_rresp), - .s_axi_rlast(axi4in_axi_rlast), - .s_axi_rvalid(axi4in_axi_rvalid), - .s_axi_rready(axi4in_axi_rready), - - // AXI4Lite Out - .m_axi_awaddr(SDCin_axi_awaddr), - .m_axi_awprot(SDCin_axi_awprot), - .m_axi_awvalid(SDCin_axi_awvalid), - .m_axi_awready(SDCin_axi_awready), - .m_axi_wdata(SDCin_axi_wdata), - .m_axi_wstrb(SDCin_axi_wstrb), - .m_axi_wvalid(SDCin_axi_wvalid), - .m_axi_wready(SDCin_axi_wready), - .m_axi_bresp(SDCin_axi_bresp), - .m_axi_bvalid(SDCin_axi_bvalid), - .m_axi_bready(SDCin_axi_bready), - .m_axi_araddr(SDCin_axi_araddr), - .m_axi_arprot(SDCin_axi_arprot), - .m_axi_arvalid(SDCin_axi_arvalid), - .m_axi_arready(SDCin_axi_arready), - .m_axi_rdata(SDCin_axi_rdata), - .m_axi_rresp(SDCin_axi_rresp), - .m_axi_rvalid(SDCin_axi_rvalid), - .m_axi_rready(SDCin_axi_rready) - - ); - - - sdc_controller axiSDC - (.clock(CPUCLK), - .async_resetn(peripheral_aresetn), - - // Slave Interface - .s_axi_awaddr({8'b0, SDCin_axi_awaddr[7:0]}), - .s_axi_awvalid(SDCin_axi_awvalid), - .s_axi_awready(SDCin_axi_awready), - .s_axi_wdata(SDCin_axi_wdata), - .s_axi_wvalid(SDCin_axi_wvalid), - .s_axi_wready(SDCin_axi_wready), - .s_axi_bresp(SDCin_axi_bresp), - .s_axi_bvalid(SDCin_axi_bvalid), - .s_axi_bready(SDCin_axi_bready), - .s_axi_araddr({8'b0, SDCin_axi_araddr[7:0]}), - .s_axi_arvalid(SDCin_axi_arvalid), - .s_axi_arready(SDCin_axi_arready), - .s_axi_rdata(SDCin_axi_rdata), - .s_axi_rresp(SDCin_axi_rresp), - .s_axi_rvalid(SDCin_axi_rvalid), - .s_axi_rready(SDCin_axi_rready), - - // Master Interface - .m_axi_awaddr(SDCout_axi_awaddr), - .m_axi_awlen(SDCout_axi_awlen), - .m_axi_awvalid(SDCout_axi_awvalid), - .m_axi_awready(SDCout_axi_awready), - .m_axi_wdata(SDCout_axi_wdata), - .m_axi_wlast(SDCout_axi_wlast), - .m_axi_wvalid(SDCout_axi_wvalid), - .m_axi_wready(SDCout_axi_wready), - .m_axi_bresp(SDCout_axi_bresp), - .m_axi_bvalid(SDCout_axi_bvalid), - .m_axi_bready(SDCout_axi_bready), - .m_axi_araddr(SDCout_axi_araddr), - .m_axi_arlen(SDCout_axi_arlen), - .m_axi_arvalid(SDCout_axi_arvalid), - .m_axi_arready(SDCout_axi_arready), - .m_axi_rdata(SDCout_axi_rdata), - .m_axi_rlast(SDCout_axi_rlast), - .m_axi_rresp(SDCout_axi_rresp), - .m_axi_rvalid(SDCout_axi_rvalid), - .m_axi_rready(SDCout_axi_rready), - - // SDC interface - //.sdio_cmd(1'b0), - //.sdio_dat(4'b0), - //.sdio_cd(1'b0) - - .sd_dat_reg_t(sd_dat_reg_t), - .sd_dat_reg_o(sd_dat_reg_o), - .sd_dat_i(sd_dat_i), - - .sd_cmd_reg_t(sd_cmd_reg_t), - .sd_cmd_reg_o(sd_cmd_reg_o), - .sd_cmd_i(sd_cmd_i), - - .sdio_clk(SDCCLK), - .sdio_cd(SDCCD), - - .interrupt(SDCIntr) - ); - - xlnx_axi_dwidth_conv_32to64 axi_conv_up - (.s_axi_aclk(CPUCLK), - .s_axi_aresetn(peripheral_aresetn), - - // Slave interface - .s_axi_awaddr(SDCout_axi_awaddr), - .s_axi_awlen(SDCout_axi_awlen), - .s_axi_awsize(3'b010), - .s_axi_awburst(2'b01), - .s_axi_awlock(1'b0), - .s_axi_awcache(4'b0), - .s_axi_awprot(3'b0), - .s_axi_awregion(4'b0), - .s_axi_awqos(4'b0), - .s_axi_awvalid(SDCout_axi_awvalid), - .s_axi_awready(SDCout_axi_awready), - .s_axi_wdata(SDCout_axi_wdata), - .s_axi_wstrb(8'b11111111), - .s_axi_wlast(SDCout_axi_wlast), - .s_axi_wvalid(SDCout_axi_wvalid), - .s_axi_wready(SDCout_axi_wready), - .s_axi_bresp(SDCout_axi_bresp), - .s_axi_bvalid(SDCout_axi_bvalid), - .s_axi_bready(SDCout_axi_bready), - .s_axi_araddr(SDCout_axi_araddr), - .s_axi_arlen(SDCout_axi_arlen), - .s_axi_arsize(3'b010), - .s_axi_arburst(2'b01), - .s_axi_arlock(1'b0), - .s_axi_arcache(4'b0), - .s_axi_arprot(3'b0), - .s_axi_arregion(4'b0), - .s_axi_arqos(4'b0), - .s_axi_arvalid(SDCout_axi_arvalid), - .s_axi_arready(SDCout_axi_arready), - .s_axi_rdata(SDCout_axi_rdata), - .s_axi_rresp(SDCout_axi_rresp), - .s_axi_rlast(SDCout_axi_rlast), - .s_axi_rvalid(SDCout_axi_rvalid), - .s_axi_rready(SDCout_axi_rready), - - // Master interface - .m_axi_awaddr(m01_axi_awaddr), - .m_axi_awlen(m01_axi_awlen), - .m_axi_awsize(m01_axi_awsize), - .m_axi_awburst(m01_axi_awburst), - .m_axi_awlock(m01_axi_awlock), - .m_axi_awcache(m01_axi_awcache), - .m_axi_awprot(m01_axi_awprot), - .m_axi_awregion(m01_axi_awregion), - .m_axi_awqos(m01_axi_awqos), - .m_axi_awvalid(m01_axi_awvalid), - .m_axi_awready(m01_axi_awready), - .m_axi_wdata(m01_axi_wdata), - .m_axi_wstrb(m01_axi_wstrb), - .m_axi_wlast(m01_axi_wlast), - .m_axi_wvalid(m01_axi_wvalid), - .m_axi_wready(m01_axi_wready), - .m_axi_bresp(m01_axi_bresp), - .m_axi_bvalid(m01_axi_bvalid), - .m_axi_bready(m01_axi_bready), - .m_axi_araddr(m01_axi_araddr), - .m_axi_arlen(m01_axi_arlen), - .m_axi_arsize(m01_axi_arsize), - .m_axi_arburst(m01_axi_arburst), - .m_axi_arlock(m01_axi_arlock), - .m_axi_arcache(m01_axi_arcache), - .m_axi_arprot(m01_axi_arprot), - .m_axi_arregion(m01_axi_arregion), - .m_axi_arqos(m01_axi_arqos), - .m_axi_arvalid(m01_axi_arvalid), - .m_axi_arready(m01_axi_arready), - .m_axi_rdata(m01_axi_rdata), - .m_axi_rresp(m01_axi_rresp), - .m_axi_rlast(m01_axi_rlast), - .m_axi_rvalid(m01_axi_rvalid), - .m_axi_rready(m01_axi_rready) - ); - - // End SDC signals -------------------------------------------- - - xlnx_axi_clock_converter xlnx_axi_clock_converter_0 + clkconverter clkconverter (.s_axi_aclk(CPUCLK), .s_axi_aresetn(peripheral_aresetn), - .s_axi_awid(s00_axi_awid), - .s_axi_awlen(s00_axi_awlen), - .s_axi_awsize(s00_axi_awsize), - .s_axi_awburst(s00_axi_awburst), - .s_axi_awcache(s00_axi_awcache), - .s_axi_awaddr(s00_axi_awaddr[30:0] ), - .s_axi_awprot(s00_axi_awprot), + .s_axi_awid(m_axi_awid), + .s_axi_awlen(m_axi_awlen), + .s_axi_awsize(m_axi_awsize), + .s_axi_awburst(m_axi_awburst), + .s_axi_awcache(m_axi_awcache), + .s_axi_awaddr(m_axi_awaddr[30:0] ), + .s_axi_awprot(m_axi_awprot), .s_axi_awregion(4'b0), // this could be a bug. bridge does not have these outputs .s_axi_awqos(4'b0), // this could be a bug. bridge does not have these outputs - .s_axi_awvalid(s00_axi_awvalid), - .s_axi_awready(s00_axi_awready), - .s_axi_awlock(s00_axi_awlock), - .s_axi_wdata(s00_axi_wdata), - .s_axi_wstrb(s00_axi_wstrb), - .s_axi_wlast(s00_axi_wlast), - .s_axi_wvalid(s00_axi_wvalid), - .s_axi_wready(s00_axi_wready), - .s_axi_bid(s00_axi_bid), - .s_axi_bresp(s00_axi_bresp), - .s_axi_bvalid(s00_axi_bvalid), - .s_axi_bready(s00_axi_bready), - .s_axi_arid(s00_axi_arid), - .s_axi_arlen(s00_axi_arlen), - .s_axi_arsize(s00_axi_arsize), - .s_axi_arburst(s00_axi_arburst), - .s_axi_arprot(s00_axi_arprot), + .s_axi_awvalid(m_axi_awvalid), + .s_axi_awready(m_axi_awready), + .s_axi_awlock(m_axi_awlock), + .s_axi_wdata(m_axi_wdata), + .s_axi_wstrb(m_axi_wstrb), + .s_axi_wlast(m_axi_wlast), + .s_axi_wvalid(m_axi_wvalid), + .s_axi_wready(m_axi_wready), + .s_axi_bid(m_axi_bid), + .s_axi_bresp(m_axi_bresp), + .s_axi_bvalid(m_axi_bvalid), + .s_axi_bready(m_axi_bready), + .s_axi_arid(m_axi_arid), + .s_axi_arlen(m_axi_arlen), + .s_axi_arsize(m_axi_arsize), + .s_axi_arburst(m_axi_arburst), + .s_axi_arprot(m_axi_arprot), .s_axi_arregion(4'b0), // this could be a bug. bridge does not have these outputs .s_axi_arqos(4'b0), // this could be a bug. bridge does not have these outputs - .s_axi_arcache(s00_axi_arcache), - .s_axi_arvalid(s00_axi_arvalid), - .s_axi_araddr(s00_axi_araddr[30:0]), - .s_axi_arlock(s00_axi_arlock), - .s_axi_arready(s00_axi_arready), - .s_axi_rid(s00_axi_rid), - .s_axi_rdata(s00_axi_rdata), - .s_axi_rresp(s00_axi_rresp), - .s_axi_rvalid(s00_axi_rvalid), - .s_axi_rlast(s00_axi_rlast), - .s_axi_rready(s00_axi_rready), + .s_axi_arcache(m_axi_arcache), + .s_axi_arvalid(m_axi_arvalid), + .s_axi_araddr(m_axi_araddr[30:0]), + .s_axi_arlock(m_axi_arlock), + .s_axi_arready(m_axi_arready), + .s_axi_rid(m_axi_rid), + .s_axi_rdata(m_axi_rdata), + .s_axi_rresp(m_axi_rresp), + .s_axi_rvalid(m_axi_rvalid), + .s_axi_rlast(m_axi_rlast), + .s_axi_rready(m_axi_rready), .m_axi_aclk(BUSCLK), .m_axi_aresetn(~reset), @@ -1053,7 +354,7 @@ module fpgaTop .m_axi_rlast(BUS_axi_rlast), .m_axi_rready(BUS_axi_rready)); - xlnx_ddr4 xlnx_ddr4_c0 + ddr4 ddr4 (.c0_init_calib_complete(c0_init_calib_complete), .dbg_clk(dbg_clk), // open .c0_sys_clk_p(default_250mhz_clk1_0_p), @@ -1122,8 +423,7 @@ module fpgaTop .addn_ui_clkout1(CPUCLK), .addn_ui_clkout2(CLK208)); - - + assign RVVIStall = '0; endmodule diff --git a/fpga/src/fpgaTopArtyA7.sv b/fpga/src/fpgaTopArtyA7.sv index 9133baa25..676d4d9a7 100644 --- a/fpga/src/fpgaTopArtyA7.sv +++ b/fpga/src/fpgaTopArtyA7.sv @@ -29,183 +29,183 @@ import cvw::*; module fpgaTop #(parameter logic RVVI_SYNTH_SUPPORTED = 0) - (input default_100mhz_clk, -(* mark_debug = "true" *) input resetn, - input south_reset, + (input logic default_100mhz_clk, + input logic resetn, + input logic south_reset, // GPIO signals - input [3:0] GPI, - output [4:0] GPO, + input logic [3:0] GPI, + output logic [4:0] GPO, // UART Signals - input UARTSin, - output UARTSout, + input logic UARTSin, + output logic UARTSout, // SDC Signals connecting to an SPI peripheral - input SDCIn, - output SDCCLK, - output SDCCmd, - output SDCCS, - input SDCCD, - input SDCWP, + input logic SDCIn, + output logic SDCCLK, + output logic SDCCmd, + output logic SDCCS, + input logic SDCCD, + input logic SDCWP, /* * Ethernet: 100BASE-T MII */ - output phy_ref_clk, - input phy_rx_clk, - input [3:0] phy_rxd, - input phy_rx_dv, - input phy_rx_er, - input phy_tx_clk, - output [3:0] phy_txd, - output phy_tx_en, - input phy_col, // nc - input phy_crs, // nc - output phy_reset_n, + output logic phy_ref_clk, + input logic phy_rx_clk, + input logic [3:0] phy_rxd, + input logic phy_rx_dv, + input logic phy_rx_er, + input logic phy_tx_clk, + output logic [3:0] phy_txd, + output logic phy_tx_en, + input logic phy_col, // nc + input logic phy_crs, // nc + output logic phy_reset_n, - inout [15:0] ddr3_dq, - inout [1:0] ddr3_dqs_n, - inout [1:0] ddr3_dqs_p, - output [13:0] ddr3_addr, - output [2:0] ddr3_ba, - output ddr3_ras_n, - output ddr3_cas_n, - output ddr3_we_n, - output ddr3_reset_n, - output [0:0] ddr3_ck_p, - output [0:0] ddr3_ck_n, - output [0:0] ddr3_cke, - output [0:0] ddr3_cs_n, - output [1:0] ddr3_dm, - output [0:0] ddr3_odt + inout logic [15:0] ddr3_dq, + inout logic [1:0] ddr3_dqs_n, + inout logic [1:0] ddr3_dqs_p, + output logic [13:0] ddr3_addr, + output logic [2:0] ddr3_ba, + output logic ddr3_ras_n, + output logic ddr3_cas_n, + output logic ddr3_we_n, + output logic ddr3_reset_n, + output logic [0:0] ddr3_ck_p, + output logic [0:0] ddr3_ck_n, + output logic [0:0] ddr3_cke, + output logic [0:0] ddr3_cs_n, + output logic [1:0] ddr3_dm, + output logic [0:0] ddr3_odt ); // MMCM Signals - wire CPUCLK; - wire c0_ddr4_ui_clk_sync_rst; - wire bus_struct_reset; - wire peripheral_reset; - wire interconnect_aresetn; - wire peripheral_aresetn; - wire mb_reset; + logic CPUCLK; + logic c0_ddr4_ui_clk_sync_rst; + logic bus_struct_reset; + logic peripheral_reset; + logic interconnect_aresetn; + logic peripheral_aresetn; + logic mb_reset; // AHB Signals from Wally - wire HCLKOpen; - wire HRESETnOpen; - wire [63:0] HRDATAEXT; - wire HREADYEXT; - wire HRESPEXT; - wire HSELEXT; - wire [55:0] HADDR; - wire [63:0] HWDATA; - wire [64/8-1:0] HWSTRB; - wire HWRITE; - wire [2:0] HSIZE; - wire [2:0] HBURST; - wire [1:0] HTRANS; - wire HREADY; - wire [3:0] HPROT; - wire HMASTLOCK; + logic HCLKOpen; + logic HRESETnOpen; + logic [63:0] HRDATAEXT; + logic HREADYEXT; + logic HRESPEXT; + logic HSELEXT; + logic [55:0] HADDR; + logic [63:0] HWDATA; + logic [64/8-1:0] HWSTRB; + logic HWRITE; + logic [2:0] HSIZE; + logic [2:0] HBURST; + logic [1:0] HTRANS; + logic HREADY; + logic [3:0] HPROT; + logic HMASTLOCK; // GPIO Signals - wire [31:0] GPIOIN, GPIOOUT, GPIOEN; + logic [31:0] GPIOIN, GPIOOUT, GPIOEN; // AHB to AXI Bridge Signals - wire [3:0] m_axi_awid; - wire [7:0] m_axi_awlen; - wire [2:0] m_axi_awsize; - wire [1:0] m_axi_awburst; - wire [3:0] m_axi_awcache; - wire [31:0] m_axi_awaddr; - wire [2:0] m_axi_awprot; - wire m_axi_awvalid; - wire m_axi_awready; - wire m_axi_awlock; - wire [63:0] m_axi_wdata; - wire [7:0] m_axi_wstrb; - wire m_axi_wlast; - wire m_axi_wvalid; - wire m_axi_wready; - wire [3:0] m_axi_bid; - wire [1:0] m_axi_bresp; - wire m_axi_bvalid; - wire m_axi_bready; - wire [3:0] m_axi_arid; - wire [7:0] m_axi_arlen; - wire [2:0] m_axi_arsize; - wire [1:0] m_axi_arburst; - wire [2:0] m_axi_arprot; - wire [3:0] m_axi_arcache; - wire m_axi_arvalid; - wire [31:0] m_axi_araddr; - wire m_axi_arlock; - wire m_axi_arready; - wire [3:0] m_axi_rid; - wire [63:0] m_axi_rdata; - wire [1:0] m_axi_rresp; - wire m_axi_rvalid; - wire m_axi_rlast; - wire m_axi_rready; + logic [3:0] m_axi_awid; + logic [7:0] m_axi_awlen; + logic [2:0] m_axi_awsize; + logic [1:0] m_axi_awburst; + logic [3:0] m_axi_awcache; + logic [31:0] m_axi_awaddr; + logic [2:0] m_axi_awprot; + logic m_axi_awvalid; + logic m_axi_awready; + logic m_axi_awlock; + logic [63:0] m_axi_wdata; + logic [7:0] m_axi_wstrb; + logic m_axi_wlast; + logic m_axi_wvalid; + logic m_axi_wready; + logic [3:0] m_axi_bid; + logic [1:0] m_axi_bresp; + logic m_axi_bvalid; + logic m_axi_bready; + logic [3:0] m_axi_arid; + logic [7:0] m_axi_arlen; + logic [2:0] m_axi_arsize; + logic [1:0] m_axi_arburst; + logic [2:0] m_axi_arprot; + logic [3:0] m_axi_arcache; + logic m_axi_arvalid; + logic [31:0] m_axi_araddr; + logic m_axi_arlock; + logic m_axi_arready; + logic [3:0] m_axi_rid; + logic [63:0] m_axi_rdata; + logic [1:0] m_axi_rresp; + logic m_axi_rvalid; + logic m_axi_rlast; + logic m_axi_rready; // AXI Signals going out of Clock Converter - wire [3:0] BUS_axi_arregion; - wire [3:0] BUS_axi_arqos; - wire [3:0] BUS_axi_awregion; - wire [3:0] BUS_axi_awqos; - wire [3:0] BUS_axi_awid; - wire [7:0] BUS_axi_awlen; - wire [2:0] BUS_axi_awsize; - wire [1:0] BUS_axi_awburst; - wire [3:0] BUS_axi_awcache; - wire [31:0] BUS_axi_awaddr; - wire [2:0] BUS_axi_awprot; - wire BUS_axi_awvalid; - wire BUS_axi_awready; - wire BUS_axi_awlock; - wire [63:0] BUS_axi_wdata; - wire [7:0] BUS_axi_wstrb; - wire BUS_axi_wlast; - wire BUS_axi_wvalid; - wire BUS_axi_wready; - wire [3:0] BUS_axi_bid; - wire [1:0] BUS_axi_bresp; - wire BUS_axi_bvalid; - wire BUS_axi_bready; - wire [3:0] BUS_axi_arid; - wire [7:0] BUS_axi_arlen; - wire [2:0] BUS_axi_arsize; - wire [1:0] BUS_axi_arburst; - wire [2:0] BUS_axi_arprot; - wire [3:0] BUS_axi_arcache; - wire BUS_axi_arvalid; - wire [31:0] BUS_axi_araddr; - wire BUS_axi_arlock; - wire BUS_axi_arready; - wire [3:0] BUS_axi_rid; - wire [63:0] BUS_axi_rdata; - wire [1:0] BUS_axi_rresp; - wire BUS_axi_rvalid; - wire BUS_axi_rlast; - wire BUS_axi_rready; + logic [3:0] BUS_axi_arregion; + logic [3:0] BUS_axi_arqos; + logic [3:0] BUS_axi_awregion; + logic [3:0] BUS_axi_awqos; + logic [3:0] BUS_axi_awid; + logic [7:0] BUS_axi_awlen; + logic [2:0] BUS_axi_awsize; + logic [1:0] BUS_axi_awburst; + logic [3:0] BUS_axi_awcache; + logic [31:0] BUS_axi_awaddr; + logic [2:0] BUS_axi_awprot; + logic BUS_axi_awvalid; + logic BUS_axi_awready; + logic BUS_axi_awlock; + logic [63:0] BUS_axi_wdata; + logic [7:0] BUS_axi_wstrb; + logic BUS_axi_wlast; + logic BUS_axi_wvalid; + logic BUS_axi_wready; + logic [3:0] BUS_axi_bid; + logic [1:0] BUS_axi_bresp; + logic BUS_axi_bvalid; + logic BUS_axi_bready; + logic [3:0] BUS_axi_arid; + logic [7:0] BUS_axi_arlen; + logic [2:0] BUS_axi_arsize; + logic [1:0] BUS_axi_arburst; + logic [2:0] BUS_axi_arprot; + logic [3:0] BUS_axi_arcache; + logic BUS_axi_arvalid; + logic [31:0] BUS_axi_araddr; + logic BUS_axi_arlock; + logic BUS_axi_arready; + logic [3:0] BUS_axi_rid; + logic [63:0] BUS_axi_rdata; + logic [1:0] BUS_axi_rresp; + logic BUS_axi_rvalid; + logic BUS_axi_rlast; + logic BUS_axi_rready; - wire BUSCLK; - wire sdio_reset_open; + logic BUSCLK; + logic sdio_reset_open; - wire c0_init_calib_complete; - wire dbg_clk; - wire [511 : 0] dbg_bus; - wire ui_clk_sync_rst; + logic c0_init_calib_complete; + logic dbg_clk; + logic [511 : 0] dbg_bus; + logic ui_clk_sync_rst; - wire CLK208; - wire clk167; - wire clk200; + logic CLK208; + logic clk167; + logic clk200; - wire app_sr_active; - wire app_ref_ack; - wire app_zq_ack; - wire mmcm_locked; - wire [11:0] device_temp; - wire mmcm1_locked; + logic app_sr_active; + logic app_ref_ack; + logic app_zq_ack; + logic mmcm_locked; + logic [11:0] device_temp; + logic mmcm1_locked; (* mark_debug = "true" *) logic RVVIStall; @@ -225,7 +225,7 @@ module fpgaTop #(parameter logic RVVI_SYNTH_SUPPORTED = 0) // 2. a second clock which is 200 MHz // Wally requires a slower clock. At this point I don't know what speed the atrix 7 will run so I'm initially targetting 25Mhz. // the mig will output a clock at 1/4 the sys clock or 41Mhz which might work with wally so we may be able to simplify the logic a lot. - xlnx_mmcm xln_mmcm(.clk_out1(clk167), + mmcm mmcm(.clk_out1(clk167), .clk_out2(clk200), .clk_out3(CPUCLK), .clk_out4(phy_ref_clk), @@ -236,7 +236,7 @@ module fpgaTop #(parameter logic RVVI_SYNTH_SUPPORTED = 0) // reset controller XILINX IP - xlnx_proc_sys_reset xlnx_proc_sys_reset_0 + sysrst sysrst (.slowest_sync_clk(CPUCLK), .ext_reset_in(1'b0), .aux_reset_in(south_reset), @@ -262,7 +262,7 @@ module fpgaTop #(parameter logic RVVI_SYNTH_SUPPORTED = 0) // ahb lite to axi bridge - xlnx_ahblite_axi_bridge xlnx_ahblite_axi_bridge_0 + ahbaxibridge ahbaxibridge (.s_ahb_hclk(CPUCLK), .s_ahb_hresetn(peripheral_aresetn), .s_ahb_hsel(HSELEXT), @@ -314,7 +314,7 @@ module fpgaTop #(parameter logic RVVI_SYNTH_SUPPORTED = 0) .m_axi_rready(m_axi_rready)); // AXI Clock Converter - xlnx_axi_clock_converter xlnx_axi_clock_converter_0 + clkconverter clkconverter (.s_axi_aclk(CPUCLK), .s_axi_aresetn(peripheral_aresetn), .s_axi_awid(m_axi_awid), @@ -400,7 +400,7 @@ module fpgaTop #(parameter logic RVVI_SYNTH_SUPPORTED = 0) .m_axi_rready(BUS_axi_rready)); // DDR3 Controller - xlnx_ddr3 xlnx_ddr3_c0 + ddr3 ddr3 ( // ddr3 I/O .ddr3_dq(ddr3_dq), diff --git a/fpga/zsbl/boot.c b/fpga/zsbl/boot.c index e98eda2c1..b21c49f48 100644 --- a/fpga/zsbl/boot.c +++ b/fpga/zsbl/boot.c @@ -153,7 +153,7 @@ void copyFlash(QWORD address, QWORD * Dst, DWORD numBlocks) { int ret = 0; // Initialize UART for messages - init_uart(20000000, 115200); + init_uart(SYSTEMCLOCK, 115200); // Print the wally banner print_uart(BANNER); diff --git a/linux/devicetree/wally-artya7.dts b/linux/devicetree/wally-artya7.dts index 99b8ff00d..5b0580695 100644 --- a/linux/devicetree/wally-artya7.dts +++ b/linux/devicetree/wally-artya7.dts @@ -21,8 +21,8 @@ cpus { #address-cells = <0x01>; #size-cells = <0x00>; - clock-frequency = <0x1312D00>; - timebase-frequency = <0x1312D00>; + clock-frequency = <0x17D7840>; + timebase-frequency = <0x17D7840>; cpu@0 { phandle = <0x01>; @@ -54,7 +54,7 @@ refclk: refclk { #clock-cells = <0>; compatible = "fixed-clock"; - clock-frequency = <0x1312D00>; + clock-frequency = <0x17D7840>; clock-output-names = "xtal"; }; @@ -73,7 +73,7 @@ uart@10000000 { interrupts = <0x0a>; interrupt-parent = <0x03>; - clock-frequency = <0x1312D00>; + clock-frequency = <0x17D7840>; reg = <0x00 0x10000000 0x00 0x100>; compatible = "ns16550a"; }; diff --git a/linux/devicetree/wally-vcu108.dts b/linux/devicetree/wally-vcu108.dts index 8c9182c6c..ef3694066 100644 --- a/linux/devicetree/wally-vcu108.dts +++ b/linux/devicetree/wally-vcu108.dts @@ -9,7 +9,7 @@ chosen { linux,initrd-end = <0x85c43a00>; linux,initrd-start = <0x84200000>; - bootargs = "console=ttyS0,115200 root=/dev/vda ro"; + bootargs = "root=/dev/vda ro console=ttyS0,115200 loglevel=7"; stdout-path = "/soc/uart@10000000"; }; @@ -21,8 +21,8 @@ cpus { #address-cells = <0x01>; #size-cells = <0x00>; - clock-frequency = <0x14FB180>; - timebase-frequency = <0x14FB180>; + clock-frequency = <0x2FAF080>; + timebase-frequency = <0x2FAF080>; cpu@0 { phandle = <0x01>; @@ -31,6 +31,9 @@ status = "okay"; compatible = "riscv"; riscv,isa = "rv64imafdcsu"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "sstc", "svinval", "svnapot", "svpbmt", "zba", "zbb", "zbc", "zbs", "zicbom", "zicbop", "zicbopz", "zicntr", "zicsr", "zifencei", "zihpm"; + riscv,cbom-block-size = <64>; mmu-type = "riscv,sv48"; interrupt-controller { @@ -48,10 +51,29 @@ compatible = "simple-bus"; ranges; + refclk: refclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0x2FAF080>; + clock-output-names = "xtal"; + }; + + gpio0: gpio@10060000 { + compatible = "sifive,gpio0"; + interrupt-parent = <0x03>; + interrupts = <3>; + reg = <0x00 0x10060000 0x00 0x1000>; + reg-names = "control"; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + uart@10000000 { interrupts = <0x0a>; interrupt-parent = <0x03>; - clock-frequency = <0x14FB180>; + clock-frequency = <0x2FAF080>; reg = <0x00 0x10000000 0x00 0x100>; compatible = "ns16550a"; }; @@ -67,18 +89,24 @@ #address-cells = <0x00>; }; - mmc@13000 { - interrupts = <0x14>; - compatible = "riscv,axi-sd-card-1.0"; - reg = <0x00 0x13000 0x00 0x7F>; - fifo-depth = <256>; - bus-width = <4>; + spi@13000 { + compatible = "sifive,spi0"; interrupt-parent = <0x03>; - clock = <0x14FB180>; - max-frequency = <0xA7D8C0>; - cap-sd-highspeed; - cap-mmc-highspeed; - no-sdio; + interrupts = <0x14>; + reg = <0x0 0x13000 0x0 0x1000>; + reg-names = "control"; + clocks = <&refclk>; + + #address-cells = <1>; + #size-cells = <0>; + mmc@0 { + compatible = "mmc-spi-slot"; + reg = <0>; + spi-max-frequency = <5000000>; + voltage-ranges = <3300 3300>; + disable-wp; + // gpios = <&gpio0 6 1>; + }; }; clint@2000000 {