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Resolved all CacheSim.py vs Wally mismaches.

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This commit is contained in:
Rose Thompson 2024-11-12 17:24:06 -06:00
parent ea2b69e1e7
commit 8659d6efdb
2 changed files with 8 additions and 7 deletions
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2
sim/rv64gc_CacheSim.py
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@ -56,7 +56,7 @@ tests64gc = ["coverage64gc", "arch64i", "arch64priv", "arch64c", "arch64m", "ar
# arch64i is the most interesting case. Uncomment line below to run just that case # arch64i is the most interesting case. Uncomment line below to run just that case
#tests64gc = ["arch64i"] #tests64gc = ["arch64i"]
#tests64gc = ["coverage64gc"] #tests64gc = ["coverage64gc"]
tests64gc = ["wally64priv"] #tests64gc = ["wally64priv"]
cachetypes = ["ICache", "DCache"] cachetypes = ["ICache", "DCache"]
simdir = os.path.expandvars("$WALLY/sim") simdir = os.path.expandvars("$WALLY/sim")

13
testbench/common/loggers.sv
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@ -210,15 +210,16 @@ module loggers import cvw::*; #(parameter cvw_t P,
dut.core.lsu.LSUAtomicM[1] ? "A" : dut.core.lsu.LSUAtomicM[1] ? "A" :
dut.core.lsu.bus.dcache.CacheRWM == 2'b10 ? "R" : dut.core.lsu.bus.dcache.CacheRWM == 2'b10 ? "R" :
dut.core.lsu.bus.dcache.CacheRWM == 2'b01 ? "W" : dut.core.lsu.bus.dcache.CacheRWM == 2'b01 ? "W" :
dut.core.lsu.bus.dcache.dcache.CMOpM == 4'b1000 ? "Z" : // cmo.zero dut.core.lsu.bus.dcache.dcache.CMOpM == 4'b1000 ? "Z" : // cbo.zero
dut.core.lsu.bus.dcache.dcache.CMOpM == 4'b0001 ? "V" : // cmo.inval should just clear the valid and dirty bits dut.core.lsu.bus.dcache.dcache.CMOpM == 4'b0001 ? "V" : // cbo.inval should just clear the valid and dirty bits
dut.core.lsu.bus.dcache.dcache.CMOpM == 4'b0010 ? "C" : // cmo.clean should act like a read in terms of the lru, but clears the dirty bit dut.core.lsu.bus.dcache.dcache.CMOpM == 4'b0010 ? "C" : // cbo.clean should act like a read in terms of the lru, but clears the dirty bit
dut.core.lsu.bus.dcache.dcache.CMOpM == 4'b0100 ? "L" : // cmo.flush should just clear and the valid and drity bits dut.core.lsu.bus.dcache.dcache.CMOpM == 4'b0100 ? "L" : // cbo.flush should just clear and the valid and drity bits
"NULL"; "NULL";
end end
assign Enabled = (dut.core.lsu.bus.dcache.dcache.cachefsm.LRUWriteEn | AccessTypeString == "Z" | assign Enabled = (dut.core.lsu.bus.dcache.dcache.cachefsm.LRUWriteEn |
((AccessTypeString == "C" | AccessTypeString == "L" | AccessTypeString == "V") & dut.core.lsu.bus.dcache.dcache.cachefsm.CacheStall == 0)) & // don't include cbo.zero as it uses LRUWriteEn to update the LRU and would be double counted.
((AccessTypeString == "C" | AccessTypeString == "L" | AccessTypeString == "V") & ~dut.core.lsu.bus.dcache.dcache.cachefsm.CacheStall)) &
~dut.core.lsu.bus.dcache.dcache.cachefsm.FlushStage & ~dut.core.lsu.bus.dcache.dcache.cachefsm.FlushStage &
dut.core.lsu.dmmu.dmmu.pmachecker.Cacheable & dut.core.lsu.dmmu.dmmu.pmachecker.Cacheable &
dut.core.lsu.bus.dcache.dcache.cachefsm.CacheEn & dut.core.lsu.bus.dcache.dcache.cachefsm.CacheEn &