From 8659d6efdb48e08d0a1f989ac1b03979656df3bb Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Tue, 12 Nov 2024 17:24:06 -0600 Subject: [PATCH] Resolved all CacheSim.py vs Wally mismaches. --- sim/rv64gc_CacheSim.py | 2 +- testbench/common/loggers.sv | 13 +++++++------ 2 files changed, 8 insertions(+), 7 deletions(-) diff --git a/sim/rv64gc_CacheSim.py b/sim/rv64gc_CacheSim.py index 6f9d575e1..5fe281bb4 100755 --- a/sim/rv64gc_CacheSim.py +++ b/sim/rv64gc_CacheSim.py @@ -56,7 +56,7 @@ tests64gc = ["coverage64gc", "arch64i", "arch64priv", "arch64c", "arch64m", "ar # arch64i is the most interesting case. Uncomment line below to run just that case #tests64gc = ["arch64i"] #tests64gc = ["coverage64gc"] -tests64gc = ["wally64priv"] +#tests64gc = ["wally64priv"] cachetypes = ["ICache", "DCache"] simdir = os.path.expandvars("$WALLY/sim") diff --git a/testbench/common/loggers.sv b/testbench/common/loggers.sv index 0307675d6..2884081ff 100644 --- a/testbench/common/loggers.sv +++ b/testbench/common/loggers.sv @@ -210,15 +210,16 @@ module loggers import cvw::*; #(parameter cvw_t P, dut.core.lsu.LSUAtomicM[1] ? "A" : dut.core.lsu.bus.dcache.CacheRWM == 2'b10 ? "R" : dut.core.lsu.bus.dcache.CacheRWM == 2'b01 ? "W" : - dut.core.lsu.bus.dcache.dcache.CMOpM == 4'b1000 ? "Z" : // cmo.zero - dut.core.lsu.bus.dcache.dcache.CMOpM == 4'b0001 ? "V" : // cmo.inval should just clear the valid and dirty bits - dut.core.lsu.bus.dcache.dcache.CMOpM == 4'b0010 ? "C" : // cmo.clean should act like a read in terms of the lru, but clears the dirty bit - dut.core.lsu.bus.dcache.dcache.CMOpM == 4'b0100 ? "L" : // cmo.flush should just clear and the valid and drity bits + dut.core.lsu.bus.dcache.dcache.CMOpM == 4'b1000 ? "Z" : // cbo.zero + dut.core.lsu.bus.dcache.dcache.CMOpM == 4'b0001 ? "V" : // cbo.inval should just clear the valid and dirty bits + dut.core.lsu.bus.dcache.dcache.CMOpM == 4'b0010 ? "C" : // cbo.clean should act like a read in terms of the lru, but clears the dirty bit + dut.core.lsu.bus.dcache.dcache.CMOpM == 4'b0100 ? "L" : // cbo.flush should just clear and the valid and drity bits "NULL"; end - assign Enabled = (dut.core.lsu.bus.dcache.dcache.cachefsm.LRUWriteEn | AccessTypeString == "Z" | - ((AccessTypeString == "C" | AccessTypeString == "L" | AccessTypeString == "V") & dut.core.lsu.bus.dcache.dcache.cachefsm.CacheStall == 0)) & + assign Enabled = (dut.core.lsu.bus.dcache.dcache.cachefsm.LRUWriteEn | + // don't include cbo.zero as it uses LRUWriteEn to update the LRU and would be double counted. + ((AccessTypeString == "C" | AccessTypeString == "L" | AccessTypeString == "V") & ~dut.core.lsu.bus.dcache.dcache.cachefsm.CacheStall)) & ~dut.core.lsu.bus.dcache.dcache.cachefsm.FlushStage & dut.core.lsu.dmmu.dmmu.pmachecker.Cacheable & dut.core.lsu.bus.dcache.dcache.cachefsm.CacheEn &