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Radix 4 sqrt passing first two tests

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cturek 2022-09-19 21:26:32 +00:00
parent 1e6bd26bb6
commit 85b3e9bfe6
4 changed files with 6 additions and 6 deletions
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2
pipelined/src/fpu/fdivsqrt.sv
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@ -1,7 +1,7 @@
///////////////////////////////////////////
// fdivsqrt.sv
//
// Written: David_Harris@hmc.edu, me@KatherineParry.com, Cedar Turek
// Written: David_Harris@hmc.edu, me@KatherineParry.com, cturek@hmc.edu
// Modified:13 January 2022
//
// Purpose: Combined Divide and Square Root Floating Point and Integer Unit

2
pipelined/src/fpu/fdivsqrtfsm.sv
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@ -1,7 +1,7 @@
///////////////////////////////////////////
// fdivsqrtfsm.sv
//
// Written: David_Harris@hmc.edu, me@KatherineParry.com, Cedar Turek
// Written: David_Harris@hmc.edu, me@KatherineParry.com, cturek@hmc.edu
// Modified:13 January 2022
//
// Purpose: Combined Divide and Square Root Floating Point and Integer Unit

6
pipelined/src/fpu/fdivsqrtpostproc.sv
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@ -1,7 +1,7 @@
///////////////////////////////////////////
// fdivsqrtpostproc.sv
//
// Written: David_Harris@hmc.edu, me@KatherineParry.com, Cedar Turek
// Written: David_Harris@hmc.edu, me@KatherineParry.com, cturek@hmc.edu
// Modified:13 January 2022
//
// Purpose: Combined Divide and Square Root Floating Point and Integer Unit
@ -71,6 +71,6 @@ module fdivsqrtpostproc(
// division takes the result from the next cycle, which is shifted to the left one more time so the square root also needs to be shifted
always_comb
if(NegSticky) QmM = FirstUM[`DIVb-(`RADIX/4):0] << SqrtM;
else QmM = FirstU[`DIVb-(`RADIX/4):0] << SqrtM;
if(NegSticky) QmM = FirstUM[`DIVb:(`RADIX/4)] << SqrtM;
else QmM = FirstU[`DIVb:(`RADIX/4)] << SqrtM;
endmodule

2
pipelined/src/fpu/fdivsqrtpreproc.sv
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@ -1,7 +1,7 @@
///////////////////////////////////////////
// fdivsqrtpreproc.sv
//
// Written: David_Harris@hmc.edu, me@KatherineParry.com, Cedar Turek
// Written: David_Harris@hmc.edu, me@KatherineParry.com, cturek@hmc.edu
// Modified:13 January 2022
//
// Purpose: Combined Divide and Square Root Floating Point and Integer Unit