diff --git a/pipelined/src/fpu/fdivsqrt.sv b/pipelined/src/fpu/fdivsqrt.sv
index 7969e0e48..2671e19f5 100644
--- a/pipelined/src/fpu/fdivsqrt.sv
+++ b/pipelined/src/fpu/fdivsqrt.sv
@@ -1,7 +1,7 @@
 ///////////////////////////////////////////
 // fdivsqrt.sv
 //
-// Written: David_Harris@hmc.edu, me@KatherineParry.com, Cedar Turek
+// Written: David_Harris@hmc.edu, me@KatherineParry.com, cturek@hmc.edu
 // Modified:13 January 2022
 //
 // Purpose: Combined Divide and Square Root Floating Point and Integer Unit
diff --git a/pipelined/src/fpu/fdivsqrtfsm.sv b/pipelined/src/fpu/fdivsqrtfsm.sv
index 9b0a23146..cc1294f2b 100644
--- a/pipelined/src/fpu/fdivsqrtfsm.sv
+++ b/pipelined/src/fpu/fdivsqrtfsm.sv
@@ -1,7 +1,7 @@
 ///////////////////////////////////////////
 // fdivsqrtfsm.sv
 //
-// Written: David_Harris@hmc.edu, me@KatherineParry.com, Cedar Turek
+// Written: David_Harris@hmc.edu, me@KatherineParry.com, cturek@hmc.edu
 // Modified:13 January 2022
 //
 // Purpose: Combined Divide and Square Root Floating Point and Integer Unit
diff --git a/pipelined/src/fpu/fdivsqrtpostproc.sv b/pipelined/src/fpu/fdivsqrtpostproc.sv
index e34ed3dbf..a4e01c7ca 100644
--- a/pipelined/src/fpu/fdivsqrtpostproc.sv
+++ b/pipelined/src/fpu/fdivsqrtpostproc.sv
@@ -1,7 +1,7 @@
 ///////////////////////////////////////////
 // fdivsqrtpostproc.sv
 //
-// Written: David_Harris@hmc.edu, me@KatherineParry.com, Cedar Turek
+// Written: David_Harris@hmc.edu, me@KatherineParry.com, cturek@hmc.edu
 // Modified:13 January 2022
 //
 // Purpose: Combined Divide and Square Root Floating Point and Integer Unit
@@ -71,6 +71,6 @@ module fdivsqrtpostproc(
 
    // division takes the result from the next cycle, which is shifted to the left one more time so the square root also needs to be shifted
   always_comb
-    if(NegSticky) QmM = FirstUM[`DIVb-(`RADIX/4):0] << SqrtM;
-    else          QmM = FirstU[`DIVb-(`RADIX/4):0]  << SqrtM;
+    if(NegSticky) QmM = FirstUM[`DIVb:(`RADIX/4)] << SqrtM;
+    else          QmM = FirstU[`DIVb:(`RADIX/4)]  << SqrtM;
 endmodule
\ No newline at end of file
diff --git a/pipelined/src/fpu/fdivsqrtpreproc.sv b/pipelined/src/fpu/fdivsqrtpreproc.sv
index b3483f328..9b3578623 100644
--- a/pipelined/src/fpu/fdivsqrtpreproc.sv
+++ b/pipelined/src/fpu/fdivsqrtpreproc.sv
@@ -1,7 +1,7 @@
 ///////////////////////////////////////////
 // fdivsqrtpreproc.sv
 //
-// Written: David_Harris@hmc.edu, me@KatherineParry.com, Cedar Turek
+// Written: David_Harris@hmc.edu, me@KatherineParry.com, cturek@hmc.edu
 // Modified:13 January 2022
 //
 // Purpose: Combined Divide and Square Root Floating Point and Integer Unit