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https://github.com/openhwgroup/cvw
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Initial testbench cleanup for Verilator
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4053eb5ba8
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@ -320,10 +320,10 @@ module testbench;
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$display("Embench Benchmark: %s is done.", tests[test]);
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$display("Embench Benchmark: %s is done.", tests[test]);
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if (riscofTest) outputfile = {pathname, tests[test], "/ref/ref.sim.output"};
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if (riscofTest) outputfile = {pathname, tests[test], "/ref/ref.sim.output"};
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else outputfile = {pathname, tests[test], ".sim.output"};
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else outputfile = {pathname, tests[test], ".sim.output"};
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outputFilePointer = $fopen(outputfile);
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outputFilePointer = $fopen(outputfile, "w");
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i = 0;
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i = 0;
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while ($unsigned(i) < $unsigned(5'd5)) begin
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while ($unsigned(i) < $unsigned(5'd5)) begin
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$fdisplayh(outputFilePointer, DCacheFlushFSM.ShadowRAM[testadr+i]);
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$fdisplay("%x %s", outputFilePointer, DCacheFlushFSM.ShadowRAM[testadr+i]);
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i = i + 1;
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i = i + 1;
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end
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end
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$fclose(outputFilePointer);
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$fclose(outputFilePointer);
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@ -574,7 +574,7 @@ module testbench;
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assign InvalEdge = dut.core.ifu.InvalidateICacheM & ~InvalDelayed;
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assign InvalEdge = dut.core.ifu.InvalidateICacheM & ~InvalDelayed;
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initial begin
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initial begin
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LogFile = $psprintf("ICache.log");
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LogFile = "ICache.log";
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file = $fopen(LogFile, "w");
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file = $fopen(LogFile, "w");
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$fwrite(file, "BEGIN %s\n", memfilename);
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$fwrite(file, "BEGIN %s\n", memfilename);
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end
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end
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@ -617,7 +617,7 @@ module testbench;
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(AccessTypeString != "NULL");
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(AccessTypeString != "NULL");
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initial begin
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initial begin
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LogFile = $psprintf("DCache.log");
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LogFile = "DCache.log";
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file = $fopen(LogFile, "w");
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file = $fopen(LogFile, "w");
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$fwrite(file, "BEGIN %s\n", memfilename);
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$fwrite(file, "BEGIN %s\n", memfilename);
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end
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end
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@ -643,7 +643,8 @@ module testbench;
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flop #(1) ResetDReg(clk, reset, resetD);
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flop #(1) ResetDReg(clk, reset, resetD);
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assign resetEdge = ~reset & resetD;
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assign resetEdge = ~reset & resetD;
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initial begin
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initial begin
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LogFile = $psprintf("branch_%s%0d.log", `BPRED_TYPE, `BPRED_SIZE);
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LogFile = "branch.log"; // will break some of Ross's research analysis scripts
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//LogFile = $psprintf("branch_%s%0d.log", `BPRED_TYPE, `BPRED_SIZE);
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file = $fopen(LogFile, "w");
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file = $fopen(LogFile, "w");
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end
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end
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always @(posedge clk) begin
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always @(posedge clk) begin
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@ -742,8 +743,7 @@ module DCacheFlushFSM
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integer i, j, k, l;
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integer i, j, k, l;
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always @(posedge clk) begin
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always @(posedge clk) begin
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if (start) begin #1
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if (start) begin
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#1
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for(i = 0; i < numlines; i++) begin
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for(i = 0; i < numlines; i++) begin
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for(j = 0; j < numways; j++) begin
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for(j = 0; j < numways; j++) begin
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for(l = 0; l < cachesramwords; l++) begin
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for(l = 0; l < cachesramwords; l++) begin
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