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https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Updated vc108 constraints for spi based sd card and setting 50 Mhz.
This commit is contained in:
Rose Thompson
parent
167878aee4
commit
842aea157c
@ -3,8 +3,9 @@
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# mmcm_clkout0 is the clock output of the DDR4 memory interface / 4.
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# This clock is not used by wally or the AHBLite Bus. However it is used by the AXI BUS on the DD4 IP.
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# create_generated_clock -name CLKDiv64_Gen -source [get_pins wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/I0] -multiply_by 1 -divide_by 2 [get_pins wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/O]
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create_generated_clock -name CLKDiv64_Gen -source [get_pins xlnx_ddr4_c0/addn_ui_clkout1] -multiply_by 1 -divide_by 1 [get_pins axiSDC/clock_posedge_reg/Q]
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# create_generated_clock -name CLKDiv64_Gen -source [get_pins #wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/I0] -multiply_by 1 -divide_by 2 [get_pins wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/O]
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#create_generated_clock -name CLKDiv64_Gen -source [get_pins ddr4_c0/addn_ui_clkout1] -multiply_by 1 -divide_by 1 [get_pins axiSDC/clock_posedge_reg/Q]
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create_generated_clock -name SPISDCClock -source [get_pins ddr4/addn_ui_clkout1] -multiply_by 1 -divide_by 1 [get_pins wallypipelinedsoc/uncore.uncore/sdc.sdc/SPICLK]
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##### GPI ####
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set_property PACKAGE_PIN E34 [get_ports {GPI[0]}]
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@ -17,7 +18,7 @@ set_property IOSTANDARD LVCMOS12 [get_ports {GPI[1]}]
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set_property IOSTANDARD LVCMOS12 [get_ports {GPI[0]}]
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set_input_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 2.000 [get_ports {GPI[*]}]
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set_input_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 2.000 [get_ports {GPI[*]}]
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set_max_delay -from [get_ports {GPI[*]}] 10.000n
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set_max_delay -from [get_ports {GPI[*]}] 10.000
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##### GPO ####
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set_property PACKAGE_PIN AT32 [get_ports {GPO[0]}]
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@ -69,15 +70,6 @@ set_property IOSTANDARD LVCMOS12 [get_ports {cpu_reset}]
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set_output_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_ports {cpu_reset}]
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set_output_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 0.000 [get_ports {cpu_reset}]
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##### calib #####
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set_property PACKAGE_PIN BA37 [get_ports calib]
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set_property IOSTANDARD LVCMOS12 [get_ports calib]
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set_output_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_ports calib]
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set_output_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 20.000 [get_ports calib]
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set_max_delay -from [get_pins xlnx_ddr4_c0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/calDone_gated_reg/C] -to [get_ports calib] 50.000
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##### ahblite_resetn #####
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set_property PACKAGE_PIN AV36 [get_ports {ahblite_resetn}]
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set_property IOSTANDARD LVCMOS12 [get_ports {ahblite_resetn}]
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@ -94,44 +86,34 @@ set_input_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 2.000 [get_port
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##### SD Card I/O #####
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# set_property PACKAGE_PIN BC14 [get_ports {SDCDat[3]}]
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# set_property IOSTANDARD LVCMOS18 [get_ports {SDCDat[3]}]
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# set_property IOSTANDARD LVCMOS18 [get_ports {SDCDat[2]}]
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# set_property IOSTANDARD LVCMOS18 [get_ports {SDCDat[1]}]
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# set_property IOSTANDARD LVCMOS18 [get_ports {SDCDat[0]}]
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# set_property PACKAGE_PIN BF7 [get_ports {SDCDat[2]}]
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# set_property PACKAGE_PIN BC13 [get_ports {SDCDat[1]}]
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# set_property PACKAGE_PIN AW16 [get_ports {SDCDat[0]}]
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# set_property IOSTANDARD LVCMOS18 [get_ports SDCCLK]
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# set_property IOSTANDARD LVCMOS18 [get_ports {SDCCmd}]
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# set_property PACKAGE_PIN BB16 [get_ports SDCCLK]
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# set_property PACKAGE_PIN BA10 [get_ports {SDCCmd}]
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# set_property PULLUP true [get_ports {SDCDat[3]}]
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# set_property PULLUP true [get_ports {SDCDat[2]}]
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# set_property PULLUP true [get_ports {SDCDat[1]}]
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# set_property PULLUP true [get_ports {SDCDat[0]}]
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# set_property PULLUP true [get_ports {SDCCmd}]
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set_output_delay -clock [get_clocks SPISDCClock] -min -add_delay 2.500 [get_ports {SDCCS}]
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set_output_delay -clock [get_clocks SPISDCClock] -max -add_delay 10.000 [get_ports {SDCCS}]
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set_input_delay -clock [get_clocks SPISDCClock] -min -add_delay 2.500 [get_ports {SDCIn}]
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set_input_delay -clock [get_clocks SPISDCClock] -max -add_delay 10.000 [get_ports {SDCIn}]
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set_output_delay -clock [get_clocks SPISDCClock] -min -add_delay 2.000 [get_ports {SDCCmd}]
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set_output_delay -clock [get_clocks SPISDCClock] -max -add_delay 6.000 [get_ports {SDCCmd}]
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set_output_delay -clock [get_clocks SPISDCClock] 0.000 [get_ports SDCCLK]
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set_property -dict {PACKAGE_PIN BC14 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {SDCDat[3]}]
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set_property -dict {PACKAGE_PIN BF7 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {SDCDat[2]}]
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set_property -dict {PACKAGE_PIN BC13 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {SDCDat[1]}]
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set_property -dict {PACKAGE_PIN AW16 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {SDCDat[0]}]
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set_property -dict {PACKAGE_PIN BC14 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {SDCCS}]
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set_property -dict {PACKAGE_PIN AW16 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {SDCIn}]
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set_property -dict {PACKAGE_PIN BA10 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {SDCCmd}]
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set_property -dict {PACKAGE_PIN AW12 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {SDCCD}]
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set_property -dict {PACKAGE_PIN BB16 IOSTANDARD LVCMOS18} [get_ports SDCCLK]
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set_property PACKAGE_PIN AW12 [get_ports SDCCD]
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set_property IOSTANDARD LVCMOS18 [get_ports SDCCD]
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set_property PULLTYPE PULLUP [get_ports SDCCD]
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set_property PACKAGE_PIN BC16 [get_ports SDCWP]
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set_property IOSTANDARD LVCMO18 [get_ports SDCWP]
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set_property PULLTYPE PULLUP [get_ports SDCWP]
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set_input_delay -clock [get_clocks CLKDiv64_Gen] -min -add_delay 2.500 [get_ports {SDCDat[*]}]
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set_input_delay -clock [get_clocks CLKDiv64_Gen] -max -add_delay 21.000 [get_ports {SDCDat[*]}]
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set_input_delay -clock [get_clocks CLKDiv64_Gen] -min -add_delay 2.500 [get_ports {SDCCmd}]
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set_input_delay -clock [get_clocks CLKDiv64_Gen] -max -add_delay 14.000 [get_ports {SDCCmd}]
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set_output_delay -clock [get_clocks CLKDiv64_Gen] -min -add_delay 2.000 [get_ports {SDCCmd}]
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set_output_delay -clock [get_clocks CLKDiv64_Gen] -max -add_delay 6.000 [get_ports {SDCCmd}]
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set_output_delay -clock [get_clocks CLKDiv64_Gen] 0.000 [get_ports SDCCLK]
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#set_input_delay -clock [get_clocks CLKDiv64_Gen] -min -add_delay 2.500 [get_ports {SDCDat[*]}]
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#set_input_delay -clock [get_clocks CLKDiv64_Gen] -max -add_delay 21.000 [get_ports {SDCDat[*]}]
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#set_input_delay -clock [get_clocks CLKDiv64_Gen] -min -add_delay 2.500 [get_ports {SDCCmd}]
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#set_input_delay -clock [get_clocks CLKDiv64_Gen] -max -add_delay 14.000 [get_ports {SDCCmd}]
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#set_output_delay -clock [get_clocks CLKDiv64_Gen] -min -add_delay 2.000 [get_ports {SDCCmd}]
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#set_output_delay -clock [get_clocks CLKDiv64_Gen] -max -add_delay 6.000 [get_ports {SDCCmd}]
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#set_output_delay -clock [get_clocks CLKDiv64_Gen] 0.000 [get_ports SDCCLK]
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@ -264,8 +246,8 @@ set_property PACKAGE_PIN D27 [get_ports {c0_ddr4_dm_dbi_n[7]}]
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set_max_delay -datapath_only -from [get_pins xlnx_ddr4_c0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/calDone_gated_reg/C] -to [get_pins xlnx_proc_sys_reset_0/U0/EXT_LPF/lpf_int_reg/D] 10.000
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set_output_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_ports c0_ddr4_reset_n]
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set_output_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 20.000 [get_ports c0_ddr4_reset_n]
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#set_output_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_ports c0_ddr4_reset_n]
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#set_output_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 20.000 [get_ports c0_ddr4_reset_n]
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@ -15,12 +15,12 @@ set_property -dict [list CONFIG.C0.ControllerType {DDR4_SDRAM} \
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CONFIG.No_Controller {1} \
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CONFIG.Phy_Only {Complete_Memory_Controller} \
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CONFIG.C0.DDR4_PhyClockRatio {4:1} \
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CONFIG.C0.DDR4_TimePeriod {1200} \
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CONFIG.C0.DDR4_TimePeriod {833} \
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CONFIG.C0.DDR4_MemoryPart {MT40A256M16GE-083E} \
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CONFIG.C0.DDR4_BurstLength {8} \
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CONFIG.C0.DDR4_BurstType {Sequential} \
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CONFIG.C0.DDR4_CasLatency {13} \
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CONFIG.C0.DDR4_CasWriteLatency {10} \
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CONFIG.C0.DDR4_CasLatency {16} \
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CONFIG.C0.DDR4_CasWriteLatency {12} \
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CONFIG.C0.DDR4_Slot {Single} \
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CONFIG.C0.DDR4_MemoryVoltage {1.2V} \
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CONFIG.C0.DDR4_DataWidth {64} \
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@ -36,14 +36,11 @@ set_property -dict [list CONFIG.C0.ControllerType {DDR4_SDRAM} \
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CONFIG.C0.DDR4_AxiIDWidth {4} \
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CONFIG.C0.DDR4_AxiAddressWidth {31} \
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CONFIG.C0.DDR4_AxiNarrowBurst {false} \
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CONFIG.C0.DDR4_CLKFBOUT_MULT {5} \
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CONFIG.C0.DDR4_DIVCLK_DIVIDE {1} \
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CONFIG.C0.DDR4_CLKOUT0_DIVIDE {6} \
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CONFIG.Reference_Clock {Differential} \
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CONFIG.ADDN_UI_CLKOUT1.INSERT_VIP {0} \
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CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {22} \
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CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {50} \
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CONFIG.ADDN_UI_CLKOUT2.INSERT_VIP {0} \
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CONFIG.ADDN_UI_CLKOUT2_FREQ_HZ {208} \
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CONFIG.ADDN_UI_CLKOUT2_FREQ_HZ {300} \
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CONFIG.ADDN_UI_CLKOUT3.INSERT_VIP {0} \
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CONFIG.ADDN_UI_CLKOUT3_FREQ_HZ {None} \
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CONFIG.ADDN_UI_CLKOUT4.INSERT_VIP {0} \
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@ -106,7 +103,7 @@ set_property -dict [list CONFIG.C0.ControllerType {DDR4_SDRAM} \
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CONFIG.C0.DDR4_CustomParts {no_file_loaded} \
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CONFIG.C0.DDR4_EN_PARITY {false} \
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CONFIG.C0.DDR4_Enable_LVAUX {false} \
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CONFIG.C0.DDR4_InputClockPeriod {3359} \
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CONFIG.C0.DDR4_InputClockPeriod {3332} \
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CONFIG.C0.DDR4_LR_SKEW_0 {0} \
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CONFIG.C0.DDR4_LR_SKEW_1 {0} \
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CONFIG.C0.DDR4_MemoryName {MainMemory} \
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@ -115,6 +112,7 @@ set_property -dict [list CONFIG.C0.ControllerType {DDR4_SDRAM} \
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CONFIG.C0.DDR4_ODT_SKEW_2 {0} \
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CONFIG.C0.DDR4_ODT_SKEW_3 {0} \
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CONFIG.C0.DDR4_OnDieTermination {RZQ/6} \
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CONFIG.C0.DDR4_OutputDriverImpedenceControl {RZQ/7} \
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CONFIG.C0.DDR4_PAR_SKEW {0} \
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CONFIG.C0.DDR4_Specify_MandD {false} \
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CONFIG.C0.DDR4_TREFI {0} \
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@ -195,7 +195,7 @@ module fpgaTop
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// reset controller XILINX IP
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xlnx_proc_sys_reset xlnx_proc_sys_reset_0
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sysrst sysrst
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(.slowest_sync_clk(CPUCLK),
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.ext_reset_in(c0_ddr4_ui_clk_sync_rst),
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.aux_reset_in(south_rst),
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@ -220,7 +220,7 @@ module fpgaTop
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.UARTSin, .UARTSout, .SDCIn, .SDCCmd, .SDCCS(SDCCSin), .SDCCLK, .ExternalStall(RVVIStall));
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// ahb lite to axi bridge
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xlnx_ahblite_axi_bridge xlnx_ahblite_axi_bridge_0
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ahbaxibridge ahbaxibridge
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(.s_ahb_hclk(CPUCLK),
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.s_ahb_hresetn(peripheral_aresetn),
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.s_ahb_hsel(HSELEXT),
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@ -271,7 +271,7 @@ module fpgaTop
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.m_axi_rlast(m_axi_rlast),
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.m_axi_rready(m_axi_rready));
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xlnx_axi_clock_converter xlnx_axi_clock_converter_0
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clkconverter clkconverter
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(.s_axi_aclk(CPUCLK),
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.s_axi_aresetn(peripheral_aresetn),
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.s_axi_awid(m_axi_awid),
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@ -356,7 +356,7 @@ module fpgaTop
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.m_axi_rlast(BUS_axi_rlast),
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.m_axi_rready(BUS_axi_rready));
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xlnx_ddr4 xlnx_ddr4_c0
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ddr4 ddr4
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(.c0_init_calib_complete(c0_init_calib_complete),
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.dbg_clk(dbg_clk), // open
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.c0_sys_clk_p(default_250mhz_clk1_0_p),
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