From 842aea157cebb6d132fc2dc50181cc71a465ff44 Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Fri, 23 Aug 2024 15:59:11 -0700 Subject: [PATCH] Updated vc108 constraints for spi based sd card and setting 50 Mhz. --- fpga/constraints/constraints-vcu108.xdc | 74 ++++++++++--------------- fpga/generator/ddr4-vcu108.tcl | 16 +++--- fpga/src/fpgaTop.sv | 10 ++-- 3 files changed, 40 insertions(+), 60 deletions(-) diff --git a/fpga/constraints/constraints-vcu108.xdc b/fpga/constraints/constraints-vcu108.xdc index 8d59509be..b30b4273c 100644 --- a/fpga/constraints/constraints-vcu108.xdc +++ b/fpga/constraints/constraints-vcu108.xdc @@ -3,8 +3,9 @@ # mmcm_clkout0 is the clock output of the DDR4 memory interface / 4. # This clock is not used by wally or the AHBLite Bus. However it is used by the AXI BUS on the DD4 IP. -# create_generated_clock -name CLKDiv64_Gen -source [get_pins wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/I0] -multiply_by 1 -divide_by 2 [get_pins wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/O] -create_generated_clock -name CLKDiv64_Gen -source [get_pins xlnx_ddr4_c0/addn_ui_clkout1] -multiply_by 1 -divide_by 1 [get_pins axiSDC/clock_posedge_reg/Q] +# create_generated_clock -name CLKDiv64_Gen -source [get_pins #wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/I0] -multiply_by 1 -divide_by 2 [get_pins wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/O] +#create_generated_clock -name CLKDiv64_Gen -source [get_pins ddr4_c0/addn_ui_clkout1] -multiply_by 1 -divide_by 1 [get_pins axiSDC/clock_posedge_reg/Q] +create_generated_clock -name SPISDCClock -source [get_pins ddr4/addn_ui_clkout1] -multiply_by 1 -divide_by 1 [get_pins wallypipelinedsoc/uncore.uncore/sdc.sdc/SPICLK] ##### GPI #### set_property PACKAGE_PIN E34 [get_ports {GPI[0]}] @@ -17,7 +18,7 @@ set_property IOSTANDARD LVCMOS12 [get_ports {GPI[1]}] set_property IOSTANDARD LVCMOS12 [get_ports {GPI[0]}] set_input_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 2.000 [get_ports {GPI[*]}] set_input_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 2.000 [get_ports {GPI[*]}] -set_max_delay -from [get_ports {GPI[*]}] 10.000n +set_max_delay -from [get_ports {GPI[*]}] 10.000 ##### GPO #### set_property PACKAGE_PIN AT32 [get_ports {GPO[0]}] @@ -69,15 +70,6 @@ set_property IOSTANDARD LVCMOS12 [get_ports {cpu_reset}] set_output_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_ports {cpu_reset}] set_output_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 0.000 [get_ports {cpu_reset}] - -##### calib ##### -set_property PACKAGE_PIN BA37 [get_ports calib] -set_property IOSTANDARD LVCMOS12 [get_ports calib] -set_output_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_ports calib] -set_output_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 20.000 [get_ports calib] -set_max_delay -from [get_pins xlnx_ddr4_c0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/calDone_gated_reg/C] -to [get_ports calib] 50.000 - - ##### ahblite_resetn ##### set_property PACKAGE_PIN AV36 [get_ports {ahblite_resetn}] set_property IOSTANDARD LVCMOS12 [get_ports {ahblite_resetn}] @@ -94,44 +86,34 @@ set_input_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 2.000 [get_port ##### SD Card I/O ##### -# set_property PACKAGE_PIN BC14 [get_ports {SDCDat[3]}] -# set_property IOSTANDARD LVCMOS18 [get_ports {SDCDat[3]}] -# set_property IOSTANDARD LVCMOS18 [get_ports {SDCDat[2]}] -# set_property IOSTANDARD LVCMOS18 [get_ports {SDCDat[1]}] -# set_property IOSTANDARD LVCMOS18 [get_ports {SDCDat[0]}] -# set_property PACKAGE_PIN BF7 [get_ports {SDCDat[2]}] -# set_property PACKAGE_PIN BC13 [get_ports {SDCDat[1]}] -# set_property PACKAGE_PIN AW16 [get_ports {SDCDat[0]}] -# set_property IOSTANDARD LVCMOS18 [get_ports SDCCLK] -# set_property IOSTANDARD LVCMOS18 [get_ports {SDCCmd}] -# set_property PACKAGE_PIN BB16 [get_ports SDCCLK] -# set_property PACKAGE_PIN BA10 [get_ports {SDCCmd}] -# set_property PULLUP true [get_ports {SDCDat[3]}] -# set_property PULLUP true [get_ports {SDCDat[2]}] -# set_property PULLUP true [get_ports {SDCDat[1]}] -# set_property PULLUP true [get_ports {SDCDat[0]}] -# set_property PULLUP true [get_ports {SDCCmd}] +set_output_delay -clock [get_clocks SPISDCClock] -min -add_delay 2.500 [get_ports {SDCCS}] +set_output_delay -clock [get_clocks SPISDCClock] -max -add_delay 10.000 [get_ports {SDCCS}] +set_input_delay -clock [get_clocks SPISDCClock] -min -add_delay 2.500 [get_ports {SDCIn}] +set_input_delay -clock [get_clocks SPISDCClock] -max -add_delay 10.000 [get_ports {SDCIn}] +set_output_delay -clock [get_clocks SPISDCClock] -min -add_delay 2.000 [get_ports {SDCCmd}] +set_output_delay -clock [get_clocks SPISDCClock] -max -add_delay 6.000 [get_ports {SDCCmd}] +set_output_delay -clock [get_clocks SPISDCClock] 0.000 [get_ports SDCCLK] -set_property -dict {PACKAGE_PIN BC14 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {SDCDat[3]}] -set_property -dict {PACKAGE_PIN BF7 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {SDCDat[2]}] -set_property -dict {PACKAGE_PIN BC13 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {SDCDat[1]}] -set_property -dict {PACKAGE_PIN AW16 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {SDCDat[0]}] +set_property -dict {PACKAGE_PIN BC14 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {SDCCS}] +set_property -dict {PACKAGE_PIN AW16 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {SDCIn}] set_property -dict {PACKAGE_PIN BA10 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {SDCCmd}] set_property -dict {PACKAGE_PIN AW12 IOSTANDARD LVCMOS18 PULLUP true} [get_ports {SDCCD}] set_property -dict {PACKAGE_PIN BB16 IOSTANDARD LVCMOS18} [get_ports SDCCLK] +set_property PACKAGE_PIN AW12 [get_ports SDCCD] +set_property IOSTANDARD LVCMOS18 [get_ports SDCCD] +set_property PULLTYPE PULLUP [get_ports SDCCD] +set_property PACKAGE_PIN BC16 [get_ports SDCWP] +set_property IOSTANDARD LVCMO18 [get_ports SDCWP] +set_property PULLTYPE PULLUP [get_ports SDCWP] -set_input_delay -clock [get_clocks CLKDiv64_Gen] -min -add_delay 2.500 [get_ports {SDCDat[*]}] -set_input_delay -clock [get_clocks CLKDiv64_Gen] -max -add_delay 21.000 [get_ports {SDCDat[*]}] - -set_input_delay -clock [get_clocks CLKDiv64_Gen] -min -add_delay 2.500 [get_ports {SDCCmd}] -set_input_delay -clock [get_clocks CLKDiv64_Gen] -max -add_delay 14.000 [get_ports {SDCCmd}] - - -set_output_delay -clock [get_clocks CLKDiv64_Gen] -min -add_delay 2.000 [get_ports {SDCCmd}] -set_output_delay -clock [get_clocks CLKDiv64_Gen] -max -add_delay 6.000 [get_ports {SDCCmd}] - -set_output_delay -clock [get_clocks CLKDiv64_Gen] 0.000 [get_ports SDCCLK] +#set_input_delay -clock [get_clocks CLKDiv64_Gen] -min -add_delay 2.500 [get_ports {SDCDat[*]}] +#set_input_delay -clock [get_clocks CLKDiv64_Gen] -max -add_delay 21.000 [get_ports {SDCDat[*]}] +#set_input_delay -clock [get_clocks CLKDiv64_Gen] -min -add_delay 2.500 [get_ports {SDCCmd}] +#set_input_delay -clock [get_clocks CLKDiv64_Gen] -max -add_delay 14.000 [get_ports {SDCCmd}] +#set_output_delay -clock [get_clocks CLKDiv64_Gen] -min -add_delay 2.000 [get_ports {SDCCmd}] +#set_output_delay -clock [get_clocks CLKDiv64_Gen] -max -add_delay 6.000 [get_ports {SDCCmd}] +#set_output_delay -clock [get_clocks CLKDiv64_Gen] 0.000 [get_ports SDCCLK] @@ -264,8 +246,8 @@ set_property PACKAGE_PIN D27 [get_ports {c0_ddr4_dm_dbi_n[7]}] set_max_delay -datapath_only -from [get_pins xlnx_ddr4_c0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/calDone_gated_reg/C] -to [get_pins xlnx_proc_sys_reset_0/U0/EXT_LPF/lpf_int_reg/D] 10.000 -set_output_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_ports c0_ddr4_reset_n] -set_output_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 20.000 [get_ports c0_ddr4_reset_n] +#set_output_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_ports c0_ddr4_reset_n] +#set_output_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 20.000 [get_ports c0_ddr4_reset_n] diff --git a/fpga/generator/ddr4-vcu108.tcl b/fpga/generator/ddr4-vcu108.tcl index e9610cfff..63c849729 100644 --- a/fpga/generator/ddr4-vcu108.tcl +++ b/fpga/generator/ddr4-vcu108.tcl @@ -15,12 +15,12 @@ set_property -dict [list CONFIG.C0.ControllerType {DDR4_SDRAM} \ CONFIG.No_Controller {1} \ CONFIG.Phy_Only {Complete_Memory_Controller} \ CONFIG.C0.DDR4_PhyClockRatio {4:1} \ - CONFIG.C0.DDR4_TimePeriod {1200} \ + CONFIG.C0.DDR4_TimePeriod {833} \ CONFIG.C0.DDR4_MemoryPart {MT40A256M16GE-083E} \ CONFIG.C0.DDR4_BurstLength {8} \ CONFIG.C0.DDR4_BurstType {Sequential} \ - CONFIG.C0.DDR4_CasLatency {13} \ - CONFIG.C0.DDR4_CasWriteLatency {10} \ + CONFIG.C0.DDR4_CasLatency {16} \ + CONFIG.C0.DDR4_CasWriteLatency {12} \ CONFIG.C0.DDR4_Slot {Single} \ CONFIG.C0.DDR4_MemoryVoltage {1.2V} \ CONFIG.C0.DDR4_DataWidth {64} \ @@ -36,14 +36,11 @@ set_property -dict [list CONFIG.C0.ControllerType {DDR4_SDRAM} \ CONFIG.C0.DDR4_AxiIDWidth {4} \ CONFIG.C0.DDR4_AxiAddressWidth {31} \ CONFIG.C0.DDR4_AxiNarrowBurst {false} \ - CONFIG.C0.DDR4_CLKFBOUT_MULT {5} \ - CONFIG.C0.DDR4_DIVCLK_DIVIDE {1} \ - CONFIG.C0.DDR4_CLKOUT0_DIVIDE {6} \ CONFIG.Reference_Clock {Differential} \ CONFIG.ADDN_UI_CLKOUT1.INSERT_VIP {0} \ - CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {22} \ + CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {50} \ CONFIG.ADDN_UI_CLKOUT2.INSERT_VIP {0} \ - CONFIG.ADDN_UI_CLKOUT2_FREQ_HZ {208} \ + CONFIG.ADDN_UI_CLKOUT2_FREQ_HZ {300} \ CONFIG.ADDN_UI_CLKOUT3.INSERT_VIP {0} \ CONFIG.ADDN_UI_CLKOUT3_FREQ_HZ {None} \ CONFIG.ADDN_UI_CLKOUT4.INSERT_VIP {0} \ @@ -106,7 +103,7 @@ set_property -dict [list CONFIG.C0.ControllerType {DDR4_SDRAM} \ CONFIG.C0.DDR4_CustomParts {no_file_loaded} \ CONFIG.C0.DDR4_EN_PARITY {false} \ CONFIG.C0.DDR4_Enable_LVAUX {false} \ - CONFIG.C0.DDR4_InputClockPeriod {3359} \ + CONFIG.C0.DDR4_InputClockPeriod {3332} \ CONFIG.C0.DDR4_LR_SKEW_0 {0} \ CONFIG.C0.DDR4_LR_SKEW_1 {0} \ CONFIG.C0.DDR4_MemoryName {MainMemory} \ @@ -115,6 +112,7 @@ set_property -dict [list CONFIG.C0.ControllerType {DDR4_SDRAM} \ CONFIG.C0.DDR4_ODT_SKEW_2 {0} \ CONFIG.C0.DDR4_ODT_SKEW_3 {0} \ CONFIG.C0.DDR4_OnDieTermination {RZQ/6} \ + CONFIG.C0.DDR4_OutputDriverImpedenceControl {RZQ/7} \ CONFIG.C0.DDR4_PAR_SKEW {0} \ CONFIG.C0.DDR4_Specify_MandD {false} \ CONFIG.C0.DDR4_TREFI {0} \ diff --git a/fpga/src/fpgaTop.sv b/fpga/src/fpgaTop.sv index 4477c971f..dfba75ce1 100644 --- a/fpga/src/fpgaTop.sv +++ b/fpga/src/fpgaTop.sv @@ -195,7 +195,7 @@ module fpgaTop // reset controller XILINX IP - xlnx_proc_sys_reset xlnx_proc_sys_reset_0 + sysrst sysrst (.slowest_sync_clk(CPUCLK), .ext_reset_in(c0_ddr4_ui_clk_sync_rst), .aux_reset_in(south_rst), @@ -220,7 +220,7 @@ module fpgaTop .UARTSin, .UARTSout, .SDCIn, .SDCCmd, .SDCCS(SDCCSin), .SDCCLK, .ExternalStall(RVVIStall)); // ahb lite to axi bridge - xlnx_ahblite_axi_bridge xlnx_ahblite_axi_bridge_0 + ahbaxibridge ahbaxibridge (.s_ahb_hclk(CPUCLK), .s_ahb_hresetn(peripheral_aresetn), .s_ahb_hsel(HSELEXT), @@ -270,8 +270,8 @@ module fpgaTop .m_axi_rvalid(m_axi_rvalid), .m_axi_rlast(m_axi_rlast), .m_axi_rready(m_axi_rready)); - - xlnx_axi_clock_converter xlnx_axi_clock_converter_0 + + clkconverter clkconverter (.s_axi_aclk(CPUCLK), .s_axi_aresetn(peripheral_aresetn), .s_axi_awid(m_axi_awid), @@ -356,7 +356,7 @@ module fpgaTop .m_axi_rlast(BUS_axi_rlast), .m_axi_rready(BUS_axi_rready)); - xlnx_ddr4 xlnx_ddr4_c0 + ddr4 ddr4 (.c0_init_calib_complete(c0_init_calib_complete), .dbg_clk(dbg_clk), // open .c0_sys_clk_p(default_250mhz_clk1_0_p),