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Now past the CLINT issues.

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This commit is contained in:
Ross Thompson 2021-08-06 16:16:39 -05:00
parent e1319a2fbe
commit 839822d3b1
2 changed files with 12 additions and 2 deletions
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4
wally-pipelined/regression/linux-wave.do
View File

@ -450,7 +450,7 @@ add wave -noupdate /testbench/textW
add wave -noupdate /testbench/dut/hart/ieu/dp/WriteDataW add wave -noupdate /testbench/dut/hart/ieu/dp/WriteDataW
add wave -noupdate /testbench/dut/hart/ieu/dp/regf/wd3 add wave -noupdate /testbench/dut/hart/ieu/dp/regf/wd3
TreeUpdate [SetDefaultTree] TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 6} {8224344 ns} 0} {{Cursor 2} {8220387 ns} 0} WaveRestoreCursors {{Cursor 6} {10872631 ns} 0}
quietly wave cursor active 1 quietly wave cursor active 1
configure wave -namecolwidth 250 configure wave -namecolwidth 250
configure wave -valuecolwidth 297 configure wave -valuecolwidth 297
@ -466,4 +466,4 @@ configure wave -griddelta 40
configure wave -timeline 0 configure wave -timeline 0
configure wave -timelineunits ns configure wave -timelineunits ns
update update
WaveRestoreZoom {8224272 ns} {8224400 ns} WaveRestoreZoom {10872596 ns} {10872666 ns}

10
wally-pipelined/testbench/testbench-linux.sv
View File

@ -292,6 +292,11 @@ module testbench();
force dut.hart.ieu.dp.regf.wd3 = ExpectedRegValueM; force dut.hart.ieu.dp.regf.wd3 = ExpectedRegValueM;
end end
else if (ExpectedMemAdrM == 'h10000005) begin
$display("%t: Overwriting read data from CLINT.", $time);
force dut.hart.ieu.dp.ReadDataW = ExpectedMemReadDataW;
force dut.hart.ieu.dp.regf.wd3 = ExpectedRegValueM;
end
end end
end end
@ -321,6 +326,11 @@ module testbench();
release dut.hart.ieu.dp.regf.wd3; release dut.hart.ieu.dp.regf.wd3;
end end
else if (ExpectedMemAdrW == 'h10000005) begin
$display("%t: releasing force of ReadDataW.", $time);
release dut.hart.ieu.dp.ReadDataW;
release dut.hart.ieu.dp.regf.wd3;
end
if(`DEBUG_TRACE > 1) begin if(`DEBUG_TRACE > 1) begin
$display("Reg Write Address: %02d ? expected value: %02d", dut.hart.ieu.dp.regf.a3, ExpectedRegAdrW); $display("Reg Write Address: %02d ? expected value: %02d", dut.hart.ieu.dp.regf.a3, ExpectedRegAdrW);