diff --git a/wally-pipelined/regression/linux-wave.do b/wally-pipelined/regression/linux-wave.do
index d974ae9c2..0d74196c4 100644
--- a/wally-pipelined/regression/linux-wave.do
+++ b/wally-pipelined/regression/linux-wave.do
@@ -450,7 +450,7 @@ add wave -noupdate /testbench/textW
 add wave -noupdate /testbench/dut/hart/ieu/dp/WriteDataW
 add wave -noupdate /testbench/dut/hart/ieu/dp/regf/wd3
 TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 6} {8224344 ns} 0} {{Cursor 2} {8220387 ns} 0}
+WaveRestoreCursors {{Cursor 6} {10872631 ns} 0}
 quietly wave cursor active 1
 configure wave -namecolwidth 250
 configure wave -valuecolwidth 297
@@ -466,4 +466,4 @@ configure wave -griddelta 40
 configure wave -timeline 0
 configure wave -timelineunits ns
 update
-WaveRestoreZoom {8224272 ns} {8224400 ns}
+WaveRestoreZoom {10872596 ns} {10872666 ns}
diff --git a/wally-pipelined/testbench/testbench-linux.sv b/wally-pipelined/testbench/testbench-linux.sv
index bb844f84b..f94ff82c1 100644
--- a/wally-pipelined/testbench/testbench-linux.sv
+++ b/wally-pipelined/testbench/testbench-linux.sv
@@ -292,6 +292,11 @@ module testbench();
         force dut.hart.ieu.dp.regf.wd3 = ExpectedRegValueM;
       end
       
+      else if (ExpectedMemAdrM == 'h10000005) begin
+	$display("%t: Overwriting read data from CLINT.", $time);
+        force dut.hart.ieu.dp.ReadDataW = ExpectedMemReadDataW;
+	force dut.hart.ieu.dp.regf.wd3 = ExpectedRegValueM;
+      end
       
     end
   end
@@ -321,6 +326,11 @@ module testbench();
         release dut.hart.ieu.dp.regf.wd3;
       end
       
+      else if (ExpectedMemAdrW == 'h10000005) begin
+	$display("%t: releasing force of ReadDataW.", $time);
+        release dut.hart.ieu.dp.ReadDataW;
+	release dut.hart.ieu.dp.regf.wd3;
+      end
       
       if(`DEBUG_TRACE > 1) begin
 	$display("Reg Write Address: %02d ? expected value: %02d", dut.hart.ieu.dp.regf.a3, ExpectedRegAdrW);