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https://github.com/openhwgroup/cvw
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Add tests for stval and mtval
This commit is contained in:
Domenico Ottolia
parent
fed42ffe19
commit
82320033d5
@ -346,7 +346,8 @@ module testbench();
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"rv64p/WALLY-SCAUSE", "2000",
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"rv64p/WALLY-MEPC", "5000",
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"rv64p/WALLY-SEPC", "4000",
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"rv64p/WALLY-TVAL", "3000",
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"rv64p/WALLY-MTVAL", "6000",
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"rv64p/WALLY-STVAL", "4000",
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"rv64p/WALLY-MARCHID", "4000",
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"rv64p/WALLY-MIMPID", "4000",
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"rv64p/WALLY-MHARTID", "4000",
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@ -358,7 +359,8 @@ module testbench();
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"rv32p/WALLY-SCAUSE", "2000",
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"rv32p/WALLY-MEPC", "5000",
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"rv32p/WALLY-SEPC", "4000",
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"rv32p/WALLY-TVAL", "3000",
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"rv32p/WALLY-MTVAL", "5000",
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"rv32p/WALLY-STVAL", "4000",
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"rv32p/WALLY-MARCHID", "4000",
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"rv32p/WALLY-MIMPID", "4000",
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"rv32p/WALLY-MHARTID", "4000",
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@ -5,7 +5,13 @@
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# dottolia@hmc.edu 1 Mar 2021
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#
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# Generate directed and random test vectors for RISC-V Design Validation.
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#
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#
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##################################
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# DOCUMENTATION:
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# Most of the comments explaining what everything
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# does can be found in testgen-TVAL.py
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###################################
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##################################
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# libraries
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@ -274,6 +280,16 @@ for xlen in xlens:
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for line in h:
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f.write(line)
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# We need to leave at least one bit in medeleg unset so that we have a way to get
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# back to machine mode when the tests are complete (otherwise we'll only ever be able
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# to get up to supervisor mode).
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#
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# So, we define a returning instruction which will be used to cause the exception that
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# brings us into machine mode. The bit for this returning instruction is NOT set in
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# medeleg. However, this also means that we can't test that instruction. So, we have
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# two different returning instructions.
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#
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# Current code is written to only support ebreak and ecall.
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for returningInstruction in ["ebreak", "ecall"]:
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# All registers used:
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@ -290,9 +306,9 @@ for xlen in xlens:
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lines = f"""
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add x7, x6, x0
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csrr x19, mtvec
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"""
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# Not used — user mode traps are deprecated
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if testMode == "u":
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lines += f"""
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csrr x17, sedeleg
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@ -1,11 +1,19 @@
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#!/usr/bin/python3
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##################################
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# testgen-CAUSE.py
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# testgen-TVAL.py
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#
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# dottolia@hmc.edu 1 Mar 2021
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#
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# Generate directed and random test vectors for RISC-V Design Validation.
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#
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##################################
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# DOCUMENTATION:
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#
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# Most of the comments explaining what everything
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# does and the layout of the privileged tests
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# can be found in this file
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#
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###################################
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##################################
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# libraries
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@ -19,20 +27,9 @@ from random import getrandbits
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# functions
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##################################
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def randRegs():
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reg1 = randint(1,20)
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reg2 = randint(1,20)
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reg3 = randint(1,20)
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if (reg1 == 6 or reg2 == 6 or reg3 == 6 or reg1 == reg2):
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return randRegs()
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else:
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return str(reg1), str(reg2), str(reg3)
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def writeVectors(storecmd):
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global testnum
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# x23 holds the expected value
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# Illegal Instruction
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writeTest(storecmd, f, r, f"""
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.fill 1, 4, 0
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@ -40,7 +37,7 @@ def writeVectors(storecmd):
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li x23, 0
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""")
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val = (randint(0, 200) * 4) + 1
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val = (randint(0, 200) * 2) + 1
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# Load Address Misaligned
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writeTest(storecmd, f, r, f"""
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@ -49,7 +46,7 @@ def writeVectors(storecmd):
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li x23, {val}
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""")
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val = (randint(0, 200) * 4) + 1
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val = (randint(0, 200) * 2) + 1
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# Store Address Misaligned
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writeTest(storecmd, f, r, f"""
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@ -62,81 +59,44 @@ def writeVectors(storecmd):
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def writeTest(storecmd, f, r, test, expected, mode = "m", resetHander = ""):
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global testnum
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global testnum, storeAddressOffset
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trapEnd = ""
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before = ""
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if mode != "m":
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before = f"""
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li x1, 0b110000000000
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csrrc x28, mstatus, x1
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li x1, 0b{"01" if mode == "s" else "00"}0000000000
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csrrs x28, mstatus, x1
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auipc x1, 0
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addi x1, x1, 16 # x1 is now right after the mret instruction
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csrrw x27, mepc, x1
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mret
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# We're now in {mode} mode...
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"""
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trapEnd = f"""j _jend{testnum}"""
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# Setup
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# TODO: Adding 8 to x30 won't work for 32 bit?
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# x31: Old mtvec value
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# x30: trap handler address
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# x29: Old mtvec value for user/supervisor mode
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# x28: Old mstatus value
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# x27: Old mepc value
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# x26: 0 if we should execute mret normally. 1 otherwise. This allows us to stay in machine
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# x25: mcause
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# x24: mtval
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# x23: mtval expected
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# mode for the next tests
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# The code we actually change for our test
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lines = f"""
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# Testcase {testnum}
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csrrs x31, mtvec, x0
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auipc x30, 0
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addi x30, x30, 12
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j _jtest{testnum}
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# Machine trap vector
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{resetHander}
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csrrs x25, mcause, x0
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csrrs x24, mtval, x0
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csrrs x1, mepc, x0
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addi x1, x1, 4
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csrrw x0, mepc, x1
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{trapEnd}
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mret
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# Actual test
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_jtest{testnum}:
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csrrw x0, mtvec, x30
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# Start test code
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li x25, 0x7BAD
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li x24, 0x7BAD
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{before}
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{test}
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# Finished test. Reset to old mtvec
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_jend{testnum}:
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{expected}
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sub x25, x24, x23
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csrrw x0, mtvec, x31
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csrr x25, {testMode}tval
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sub x25, x25, x23
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"""
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# Boilerplate
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#
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# x28 is the address that our trap handler will jump to before returning.
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# This is where we can do our actual tests. After we're done computing and storing
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# what we want, we jump to x27, which continues with the trap handling code (look at the _j_x_trap_... labels)
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#
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lines = f"""
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la x28, _jtest{testnum}
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j _jdo{testnum}
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_jtest{testnum}:
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{lines}
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jr x27
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_jdo{testnum}:
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li x25, 0xDEADBEA7
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{test}
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"""
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# We expect x25 to be 0 always. This is because of the code we wrote at the begining
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# of this function
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expected = 0
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lines += storecmd + " x25, " + str(wordsize*testnum) + "(x6)\n"
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#lines += "RVTEST_IO_ASSERT_GPR_EQ(x7, " + str(reg2) +", "+formatstr.format(expected)+")\n"
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# Store the expected value of x25 to memory and in the .reference_output file
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lines += f"""
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{storecmd} x25, 0(x7)
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addi x7, x7, {wordsize}
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"""
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f.write(lines)
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if (xlen == 32):
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line = formatrefstr.format(expected)+"\n"
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@ -145,28 +105,17 @@ def writeTest(storecmd, f, r, test, expected, mode = "m", resetHander = ""):
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r.write(line)
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testnum = testnum+1
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# lines += storecmd + " x0" + ", " + str(wordsize*testnum) + "(x6)\n"
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# #lines += "RVTEST_IO_ASSERT_GPR_EQ(x7, " + str(reg2) +", "+formatstr.format(expected)+")\n"
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# f.write(lines)
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# if (xlen == 32):
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# line = formatrefstr.format(expected)+"\n"
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# else:
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# line = formatrefstr.format(expected % 2**32)+"\n" + formatrefstr.format(expected >> 32) + "\n"
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# r.write(line)
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# testnum = testnum+1
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##################################
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# main body
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##################################
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# change these to suite your tests
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# csrrw, csrrs, csrrc, csrrwi, csrrsi, csrrci
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author = "dottolia@hmc.edu"
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xlens = [32, 64]
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numrand = 20;
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testCount = 32;
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# setup
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seed(0xC363DDEB9173AB42) # make tests reproducible
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# Change this seed to a different constant value for every test
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seed(0xC363DAEB9193AB45) # make tests reproducible
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# generate files for each test
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for xlen in xlens:
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@ -180,47 +129,243 @@ for xlen in xlens:
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storecmd = "sd"
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wordsize = 8
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corners = [
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0x624B3E976C52DD14 % 2**xlen, 2**(xlen-1)-2, 2**(xlen-1)-1,
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2**(xlen-1), 2**(xlen-1)+1, 0xC365DDEB9173AB42 % 2**xlen, 2**(xlen)-2, 2**(xlen)-1
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]
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imperaspath = "../../../imperas-riscv-tests/riscv-test-suite/rv" + str(xlen) + "p/"
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basename = "WALLY-TVAL"
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fname = imperaspath + "src/" + basename + ".S"
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refname = imperaspath + "references/" + basename + ".reference_output"
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testnum = 0
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# testMode can be m, s, and u. User mode traps are deprecated, so this should likely just be ["m", "s"]
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for testMode in ["m", "s"]:
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imperaspath = "../../../imperas-riscv-tests/riscv-test-suite/rv" + str(xlen) + "p/"
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basename = "WALLY-" + testMode.upper() + "TVAL"
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fname = imperaspath + "src/" + basename + ".S"
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refname = imperaspath + "references/" + basename + ".reference_output"
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testnum = 0
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storeAddressOffset = 0
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# print custom header part
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f = open(fname, "w")
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r = open(refname, "w")
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line = "///////////////////////////////////////////\n"
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f.write(line)
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lines="// "+fname+ "\n// " + author + "\n"
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f.write(lines)
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line ="// Created " + str(datetime.now())
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f.write(line)
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# insert generic header
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h = open("../testgen_header.S", "r")
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for line in h:
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# print custom header part
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f = open(fname, "w")
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r = open(refname, "w")
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line = "///////////////////////////////////////////\n"
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f.write(line)
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lines="// "+fname+ "\n// " + author + "\n"
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f.write(lines)
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line ="// Created " + str(datetime.now())
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f.write(line)
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# print directed and random test vectors
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for i in range(0,numrand):
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writeVectors(storecmd)
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# insert generic header
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h = open("../testgen_header.S", "r")
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for line in h:
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f.write(line)
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# We need to leave at least one bit in medeleg unset so that we have a way to get
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# back to machine mode when the tests are complete (otherwise we'll only ever be able
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# to get up to supervisor mode).
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#
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# So, we define a returning instruction which will be used to cause the exception that
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# brings us into machine mode. The bit for this returning instruction is NOT set in
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# medeleg. However, this also means that we can't test that instruction. So, we have
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# two different returning instructions.
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#
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# Current code is written to only support ebreak and ecall.
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#
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# For testgen-TVAL, we don't need to test ebreak, so we can use that as the sole
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# returning instruction. For others, like testgen-CAUSE, we'll need to put
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# both ebreak and ecall here.
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for returningInstruction in ["ebreak"]:
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# All registers used:
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# x30: set to 1 if we should return to & stay in machine mode after trap, 0 otherwise
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# ...
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# x28: address trap handler should jump to for the test
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# x27: address the test should return to after the test
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# ...
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# x25: value to write to memory
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# ...
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# x20: intermediate value in trap handler. Don't overwrite this!
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# x19: mtvec old value
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# x18: medeleg old value
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# x17: sedeleg old value (currently unused — user mode traps deprecated)
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# x16: mideleg old value
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# ...
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# x10 - x14 can be freely written
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# ...
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# x7: copy of x6. Increment this instead of using an offset on x6.
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# this allows us to create more than 2048/wordlen tests.
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# This is the address we write results to
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# x6: Starting address we should write expected results to
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# ...
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# x1 - x5 can be freely written
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# print footer
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h = open("../testgen_footer.S", "r")
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for line in h:
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f.write(line)
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# Finish
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lines = ".fill " + str(testnum) + ", " + str(wordsize) + ", -1\n"
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lines = lines + "\nRV_COMPLIANCE_DATA_END\n"
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f.write(lines)
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f.close()
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r.close()
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# Set up x7 and store old value of mtvec
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lines = f"""
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add x7, x6, x0
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csrr x19, mtvec
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"""
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# Not used — user mode traps are deprecated
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if testMode == "u":
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lines += f"""
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csrr x17, sedeleg
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li x9, {"0b1100000000" if testMode == "u" else "0b0000000000"}
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csrs sedeleg, x9
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"""
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# Code that will jump to the test (x28 is set in writeTest above)
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testJumpCode = f"""
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auipc x27, 0
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addi x27, x27, 12
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jr x28
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"""
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# Code for handling traps in different modes
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# Some comments are inside of the below strings (prefixed with a #, as you might expected)
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lines += f"""
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# Reset x30 to 0 so we can run the tests. We'll set this to 1 when tests are completed so we stay in machine mode
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li x30, 0
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# Set up
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la x1, _j_m_trap_{returningInstruction}
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csrw mtvec, x1
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la x1, _j_s_trap_{returningInstruction}
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csrw stvec, x1
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la x1, _j_u_trap_{returningInstruction}
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# csrw utvec, x1 # user mode traps are not supported
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# Start the tests!
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j _j_t_begin_{returningInstruction}
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# Machine mode traps
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_j_m_trap_{returningInstruction}:
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{testJumpCode if testMode == "m" else "li x25, 0xBAD00003"}
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csrrs x20, mepc, x0
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addi x20, x20, 4
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csrrw x0, mepc, x20
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bnez x30, _j_all_end_{returningInstruction}
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mret
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# Supervisor mode traps
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_j_s_trap_{returningInstruction}:
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{testJumpCode if testMode == "s" else "li x25, 0xBAD00001"}
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csrrs x20, sepc, x0
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addi x20, x20, 4
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csrrw x0, sepc, x20
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bnez x30, _j_goto_machine_mode_{returningInstruction}
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sret
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# Unused: user mode traps are no longer supported
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_j_u_trap_{returningInstruction}:
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{testJumpCode if testMode == "u" else "li x25, 0xBAD00000"}
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csrrs x20, uepc, x0
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addi x20, x20, 4
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csrrw x0, uepc, x20
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bnez x30, _j_goto_supervisor_mode_{returningInstruction}
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uret
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# Currently unused. Just jumps to _j_goto_machine_mode. If you actually
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# want to implement this, you'll likely need to reset sedeleg here
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# and then cause an exception with {returningInstruction} (based on my intuition. Try that first, but I could be missing something / just wrong)
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_j_goto_supervisor_mode_{returningInstruction}:
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j _j_goto_machine_mode_{returningInstruction}
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_j_goto_machine_mode_{returningInstruction}:
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li x30, 1 # This will cause us to branch to _j_all_end_{returningInstruction} in the machine trap handler, which we'll get into by invoking...
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{returningInstruction} # ... this instruction!
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# Run the actual tests!
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_j_t_begin_{returningInstruction}:
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"""
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fromModeOptions = ["m", "s", "u"] if testMode == "m" else (["s", "u"] if testMode == "s" else ["u"])
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# We don't want to delegate our returning instruction. Otherwise, we'll have no way of getting
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# back to machine mode at the end! (and we need to be in machine mode to complete the tests)
|
||||
medelegMask = "0b1111111111110111" if returningInstruction == "ebreak" else "0b1111000011111111"
|
||||
|
||||
# Set medeleg and mideleg
|
||||
lines += f"""
|
||||
csrr x18, medeleg
|
||||
li x9, {medelegMask if testMode == "s" or testMode == "u" else "0"}
|
||||
csrw medeleg, x9
|
||||
|
||||
csrr x16, mideleg
|
||||
li x9, {"0xffffffff" if testMode == "s" or testMode == "u" else "0"}
|
||||
csrw mideleg, x9
|
||||
"""
|
||||
|
||||
f.write(lines)
|
||||
|
||||
for fromMode in fromModeOptions:
|
||||
lines = ""
|
||||
|
||||
# Code to bring us down to supervisor mode
|
||||
if fromMode == "s" or fromMode == "u":
|
||||
lines += f"""
|
||||
li x1, 0b110000000000
|
||||
csrrc x28, mstatus, x1
|
||||
li x1, 0b0100000000000
|
||||
csrrs x28, mstatus, x1
|
||||
|
||||
auipc x1, 0
|
||||
addi x1, x1, 16 # x1 is now right after the mret instruction
|
||||
csrw mepc, x1
|
||||
mret
|
||||
|
||||
# We're now in supervisor mode...
|
||||
"""
|
||||
|
||||
# Code to bring us down to user mode
|
||||
if fromMode == "u":
|
||||
lines += f"""
|
||||
|
||||
li x1, 0b110000000000
|
||||
csrrc x28, sstatus, x1
|
||||
|
||||
auipc x1, 0
|
||||
addi x1, x1, 16 # x1 is now right after the sret instruction
|
||||
csrw sepc, x1
|
||||
sret
|
||||
|
||||
# We're now in user mode...
|
||||
"""
|
||||
|
||||
f.write(lines)
|
||||
for i in range(0,testCount):
|
||||
writeVectors(storecmd)
|
||||
|
||||
|
||||
# Very end of test. Bring us back up to machine mode
|
||||
# We set x30 to 1, which will cause us to branch to _j_all_end in the
|
||||
# machine mode trap handler, before executing the mret instruction. This will
|
||||
# make us stay in machine mode.
|
||||
#
|
||||
# If we're currently in user mode, this will first bump us up to the supervisor mode
|
||||
# trap handler, which will call returningInstruction again before it's sret instruction,
|
||||
# bumping us up to machine mode
|
||||
#
|
||||
# Get into the trap handler by running returningInstruction (either an ecall or ebreak)
|
||||
f.write(f"""
|
||||
li x30, 1
|
||||
{returningInstruction}
|
||||
_j_all_end_{returningInstruction}:
|
||||
|
||||
# Reset trap handling csrs to old values
|
||||
csrw mtvec, x19
|
||||
csrw medeleg, x18
|
||||
csrw mideleg, x16
|
||||
""")
|
||||
|
||||
# print footer
|
||||
h = open("../testgen_footer.S", "r")
|
||||
for line in h:
|
||||
f.write(line)
|
||||
|
||||
# Finish
|
||||
lines = ".fill " + str(testnum) + ", " + str(wordsize) + ", -1\n"
|
||||
lines = lines + "\nRV_COMPLIANCE_DATA_END\n"
|
||||
f.write(lines)
|
||||
f.close()
|
||||
r.close()
|
||||
|
||||
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user