From 81a2fbb6d23935a12eb1d565fec6e759b5849a13 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Fri, 11 Mar 2022 13:05:47 -0600 Subject: [PATCH] mild cleanup. --- pipelined/src/cache/cache.sv | 2 -- 1 file changed, 2 deletions(-) diff --git a/pipelined/src/cache/cache.sv b/pipelined/src/cache/cache.sv index dadebc69d..02f2c0407 100644 --- a/pipelined/src/cache/cache.sv +++ b/pipelined/src/cache/cache.sv @@ -152,12 +152,10 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGWPL, WORDLEN, MUXINTER .y(WordOffsetAddr)); // *** can reduce width of mux. only need the offset. else assign WordOffsetAddr = PAdr[$clog2(LINELEN/8) - 1 : $clog2(MUXINTERVAL/8)]; - subcachelineread #(LINELEN, WORDLEN, MUXINTERVAL, LOGWPL) subcachelineread( .clk, .reset, .PAdr(WordOffsetAddr), .save, .restore, .ReadDataLine, .ReadDataWord); - ///////////////////////////////////////////////////////////////////////////////////////////// // Write Path: Write data and address. Muxes between writes from bus and writes from CPU. /////////////////////////////////////////////////////////////////////////////////////////////