added SIP, SIE, and SSTATUS to checkpoints. Can't seem to get the linux testbench to force SIP.

linux/testvector-generation/parseGDBtoTrace.py

@@ -138,9 +138,9 @@ if len(sys.argv) != 2:
     sys.exit('Error parseGDBtoTrace.py expects 1 arg:\n <interrupt filename>>')
 interruptFname = sys.argv[1]
 # reg number
-RegNumber = {'zero': 0, 'ra': 1, 'sp': 2, 'gp': 3, 'tp': 4, 't0': 5, 't1': 6, 't2': 7, 's0': 8, 's1': 9, 'a0': 10, 'a1': 11, 'a2': 12, 'a3': 13, 'a4': 14, 'a5': 15, 'a6': 16, 'a7': 17, 's2': 18, 's3': 19, 's4': 20, 's5': 21, 's6': 22, 's7': 23, 's8': 24, 's9': 25, 's10': 26, 's11': 27, 't3': 28, 't4': 29, 't5': 30, 't6': 31, 'mhartid': 32, 'mstatus': 33, 'mip': 34, 'mie': 35, 'mideleg': 36, 'medeleg': 37, 'mtvec': 38, 'stvec': 39, 'mepc': 40, 'sepc': 41, 'mcause': 42, 'scause': 43, 'mtval': 44, 'stval': 45}
+RegNumber = {'zero': 0, 'ra': 1, 'sp': 2, 'gp': 3, 'tp': 4, 't0': 5, 't1': 6, 't2': 7, 's0': 8, 's1': 9, 'a0': 10, 'a1': 11, 'a2': 12, 'a3': 13, 'a4': 14, 'a5': 15, 'a6': 16, 'a7': 17, 's2': 18, 's3': 19, 's4': 20, 's5': 21, 's6': 22, 's7': 23, 's8': 24, 's9': 25, 's10': 26, 's11': 27, 't3': 28, 't4': 29, 't5': 30, 't6': 31, 'mhartid': 32, 'mstatus': 33, 'mip': 34, 'mie': 35, 'mideleg': 36, 'medeleg': 37, 'mtvec': 38, 'stvec': 39, 'mepc': 40, 'sepc': 41, 'mcause': 42, 'scause': 43, 'mtval': 44, 'stval': 45, 'sstatus': 46, 'sip': 47, 'sie': 48}
 # initial state
-CurrentInstr = ['0', '0', None, 'other', {'zero': 0, 'ra': 0, 'sp': 0, 'gp': 0, 'tp': 0, 't0': 0, 't1': 0, 't2': 0, 's0': 0, 's1': 0, 'a0': 0, 'a1': 0, 'a2': 0, 'a3': 0, 'a4': 0, 'a5': 0, 'a6': 0, 'a7': 0, 's2': 0, 's3': 0, 's4': 0, 's5': 0, 's6': 0, 's7': 0, 's8': 0, 's9': 0, 's10': 0, 's11': 0, 't3': 0, 't4': 0, 't5': 0, 't6': 0, 'mhartid': 0, 'mstatus': 0, 'mip': 0, 'mie': 0, 'mideleg': 0, 'medeleg': 0, 'mtvec': 0, 'stvec': 0, 'mepc': 0, 'sepc': 0, 'mcause': 0, 'scause': 0, 'mtval': 0, 'stval': 0}, {}, None, None, None]
+CurrentInstr = ['0', '0', None, 'other', {'zero': 0, 'ra': 0, 'sp': 0, 'gp': 0, 'tp': 0, 't0': 0, 't1': 0, 't2': 0, 's0': 0, 's1': 0, 'a0': 0, 'a1': 0, 'a2': 0, 'a3': 0, 'a4': 0, 'a5': 0, 'a6': 0, 'a7': 0, 's2': 0, 's3': 0, 's4': 0, 's5': 0, 's6': 0, 's7': 0, 's8': 0, 's9': 0, 's10': 0, 's11': 0, 't3': 0, 't4': 0, 't5': 0, 't6': 0, 'mhartid': 0, 'mstatus': 0, 'mip': 0, 'mie': 0, 'mideleg': 0, 'medeleg': 0, 'mtvec': 0, 'stvec': 0, 'mepc': 0, 'sepc': 0, 'mcause': 0, 'scause': 0, 'mtval': 0, 'stval': 0, 'sstatus': 0, 'sip': 0, 'sie': 0}, {}, None, None, None]
 
 #with open (InputFile, 'r') as InputFileFP:
 #lines = InputFileFP.readlines()

linux/testvector-generation/parseState.py

@@ -34,7 +34,7 @@ stateGDBpath = outDir+'stateGDB.txt'
 if not os.path.exists(stateGDBpath):
     sys.exit('Error input file '+stateGDBpath+'not found')
 
-singleCSRs = ['pc','mip','mie','mscratch','mcause','mepc','mtvec','medeleg','mideleg','sscratch','scause','sepc','stvec','sedeleg','sideleg','satp','mstatus','priv']
+singleCSRs = ['pc','mip','mie','mscratch','mcause','mepc','mtvec','medeleg','mideleg','sscratch','scause','sepc','stvec','sedeleg','sideleg','satp','mstatus','priv','sie','sip','sstatus']
 # priv (current privilege mode) isn't technically a CSR but we can log it with the same machinery
 thirtyTwoBitCSRs = ['mcounteren','scounteren']
 listCSRs = ['hpmcounter','pmpaddr']

pipelined/testbench/testbench-linux.sv

@@ -141,11 +141,11 @@ module testbench;
       logic [`XLEN-1:0] ExpectedCSRArrayValue``STAGE[10:0];
   `DECLARE_TRACE_SCANNER_SIGNALS(E)
   `DECLARE_TRACE_SCANNER_SIGNALS(M)
-  integer           NextMIPexpected;
+  integer           NextMIPexpected, NextSIPexpected;
   integer           NextMepcExpected;
   // Memory stage expected values from trace
   logic             checkInstrM;
-  integer           MIPexpected;
+  integer           MIPexpected, SIPexpected;
   string            name;
   logic [`AHBW-1:0] readDataExpected;
   // Write back stage expected values from trace
@@ -168,11 +168,14 @@ module testbench;
   integer           NumCSRPostWIndex;
   logic [`XLEN-1:0] InstrCountW;
   integer           RequestDelayedMIP;
+  integer           RequestDelayedSIP;  
   integer           ForceMIPFuture;
   integer           CSRIndex;
   longint           MepcExpected;
   integer           CheckMIPFutureE;
   integer           CheckMIPFutureM;
+  integer           CheckSIPFutureE;
+  integer           CheckSIPFutureM;
   // Useful Aliases
   `define RF          dut.core.ieu.dp.regf.rf
   `define PC          dut.core.ifu.pcreg.q
@@ -185,6 +188,8 @@ module testbench;
   `define MIDELEG     `CSR_BASE.csrm.deleg.MIDELEGreg.q
   `define MIE         `CSR_BASE.csri.MIE_REGW
   `define MIP         `CSR_BASE.csri.MIP_REGW
+  `define SIE         `CSR_BASE.csri.SIE_REGW
+  `define SIP         `CSR_BASE.csri.SIP_REGW
   `define MCAUSE      `CSR_BASE.csrm.MCAUSEreg.q
   `define SCAUSE      `CSR_BASE.csrs.csrs.SCAUSEreg.q
   `define MEPC        `CSR_BASE.csrm.MEPCreg.q
@@ -197,6 +202,7 @@ module testbench;
   `define STVEC       `CSR_BASE.csrs.csrs.STVECreg.q
   `define SATP        `CSR_BASE.csrs.csrs.genblk1.SATPreg.q
   `define MSTATUS     `CSR_BASE.csrsr.MSTATUS_REGW
+  `define SSTATUS     `CSR_BASE.csrsr.SSTATUS_REGW  
   `define STATUS_TSR  `CSR_BASE.csrsr.STATUS_TSR_INT
   `define STATUS_TW   `CSR_BASE.csrsr.STATUS_TW_INT
   `define STATUS_TVM  `CSR_BASE.csrsr.STATUS_TVM_INT
@@ -297,6 +303,8 @@ module testbench;
   `INIT_CHECKPOINT_VAL(MIDELEG,    [`XLEN-1:0]);
   `INIT_CHECKPOINT_VAL(MIE,        [11:0]);
   `INIT_CHECKPOINT_VAL(MIP,        [11:0]);
+  `INIT_CHECKPOINT_VAL(SIE,        [11:0]);
+  `INIT_CHECKPOINT_VAL(SIP,        [11:0]);
   `INIT_CHECKPOINT_VAL(MCAUSE,     [`XLEN-1:0]);
   `INIT_CHECKPOINT_VAL(SCAUSE,     [`XLEN-1:0]);
   `INIT_CHECKPOINT_VAL(MEPC,       [`XLEN-1:0]);
@@ -310,6 +318,7 @@ module testbench;
   `INIT_CHECKPOINT_VAL(SATP,       [`XLEN-1:0]);
   `INIT_CHECKPOINT_VAL(PRIV,       [1:0]);
   `MAKE_CHECKPOINT_INIT_SIGNAL(MSTATUS, [`XLEN-1:0],0,0);
+  `MAKE_CHECKPOINT_INIT_SIGNAL(SSTATUS, [`XLEN-1:0],0,0);  
   // Many UART registers are difficult to initialize because under the hood
   // they are not simple registers. Instead some are generated by interesting
   // combinational blocks such that they depend upon a variety of different
@@ -463,6 +472,10 @@ module testbench;
               CheckMIPFutureE = 1; \
               NextMIPexpected = ExpectedCSRArrayValueE[NumCSRE]; \
             end \
+            if(ExpectedCSRArrayE[NumCSRE].substr(0, 2) == "sip") begin \
+              CheckSIPFutureE = 1; \
+              NextSIPexpected = ExpectedCSRArrayValueE[NumCSRE]; \
+            end \
             if(ExpectedCSRArrayE[NumCSRE].substr(0,3) == "mepc") begin \
               // $display("hello! we are here."); \
               MepcExpected = ExpectedCSRArrayValueE[NumCSRE]; \
@@ -501,6 +514,7 @@ module testbench;
     if(CheckMIPFutureE) CheckMIPFutureE <= 0;
     CheckMIPFutureM <= CheckMIPFutureE;
     if(CheckMIPFutureM) begin
+      $display("DEBUG DEBUG DEBUG DEBUG");
       // $display("%tns: ExpectedPCM %x",$time,ExpectedPCM);
       // $display("%tns: ExpectedPCE %x",$time,ExpectedPCE);
       // $display("%tns: ExpectedPCW %x",$time,ExpectedPCW);
@@ -508,9 +522,12 @@ module testbench;
         RequestDelayedMIP <= 1;
         $display("%tns: Requesting Delayed MIP. Current MEPC value is %x",$time,MepcExpected);
       end else begin // update MIP immediately
+        $display("One One One One");
         $display("%tns: Updating MIP to %x",$time,NextMIPexpected);
         MIPexpected = NextMIPexpected;
-        force dut.core.priv.priv.csr.csri.MIP_REGW = MIPexpected;
+        //force dut.core.priv.priv.csr.csri.MIP_REGW = MIPexpected;
+        //force dut.core.priv.priv.csr.csri.SIP_REGW = MIPexpected;
+        force dut.core.priv.priv.csr.csri.IP_REGW = MIPexpected;
       end
       // $display("%tn: ExpectedCSRArrayM = %p",$time,ExpectedCSRArrayM);
       // $display("%tn: ExpectedCSRArrayValueM = %p",$time,ExpectedCSRArrayValueM);
@@ -524,13 +541,54 @@ module testbench;
     if(RequestDelayedMIP & checkInstrM) begin
       $display("%tns: Executing Delayed MIP. Current MEPC value is %x",$time,dut.core.priv.priv.csr.csrm.MEPC_REGW);
       $display("%tns: Updating MIP to %x",$time,NextMIPexpected);
+      $display("Two Two Two Two");
       MIPexpected = NextMIPexpected;
-      force dut.core.priv.priv.csr.csri.MIP_REGW = MIPexpected;
+      //force dut.core.priv.priv.csr.csri.MIP_REGW = MIPexpected;
+      //force dut.core.priv.priv.csr.csri.SIP_REGW = MIPexpected;
+      force dut.core.priv.priv.csr.csri.IP_REGW = MIPexpected;
       $display("%tns: Finished Executing Delayed MIP. Current MEPC value is %x",$time,dut.core.priv.priv.csr.csrm.MEPC_REGW);
       RequestDelayedMIP = 0;
     end
   end
 
+  // SIP spoofing
+/* -----\/----- EXCLUDED -----\/-----
+  always @(posedge clk) begin
+    #1;
+    if(CheckSIPFutureE) CheckSIPFutureE <= 0;
+    CheckSIPFutureM <= CheckSIPFutureE;
+    if(CheckSIPFutureM) begin
+      // $display("%tns: ExpectedPCM %x",$time,ExpectedPCM);
+      // $display("%tns: ExpectedPCE %x",$time,ExpectedPCE);
+      // $display("%tns: ExpectedPCW %x",$time,ExpectedPCW);
+      if((ExpectedPCE != MepcExpected) & ((MepcExpected - ExpectedPCE) * (MepcExpected - ExpectedPCE) <= 200) | ~dut.core.ieu.c.InstrValidM) begin
+        RequestDelayedSIP <= 1;
+        $display("%tns: Requesting Delayed SIP. Current MEPC value is %x",$time,MepcExpected);
+      end else begin // update SIP immediately
+        $display("%tns: Updating SIP to %x",$time,NextSIPexpected);
+        SIPexpected = NextSIPexpected;
+        force dut.core.priv.priv.csr.csri.SIP_REGW = SIPexpected;
+      end
+      // $display("%tn: ExpectedCSRArrayM = %p",$time,ExpectedCSRArrayM);
+      // $display("%tn: ExpectedCSRArrayValueM = %p",$time,ExpectedCSRArrayValueM);
+      // $display("%tn: ExpectedTokens = %p",$time,ExpectedTokensM);
+      // $display("%tn: MepcExpected = %x",$time,MepcExpected);
+      // $display("%tn: ExpectedPCE = %x",$time,ExpectedPCE);
+      // $display("%tns: Difference/multiplication thing: %x",$time,(MepcExpected - ExpectedPCE) * (MepcExpected - ExpectedPCE));
+      // $display("%tn: ExpectedCSRArrayM[NumCSRM] %x",$time,ExpectedCSRArrayM[NumCSRM]);
+      // $display("%tn: ExpectedCSRArrayValueM[NumCSRM] %x",$time,ExpectedCSRArrayValueM[NumCSRM]);
+    end
+    if(RequestDelayedSIP & checkInstrM) begin
+      $display("%tns: Executing Delayed SIP. Current MEPC value is %x",$time,dut.core.priv.priv.csr.csrm.MEPC_REGW);
+      $display("%tns: Updating SIP to %x",$time,NextSIPexpected);
+      SIPexpected = NextSIPexpected;
+      force dut.core.priv.priv.csr.csri.SIP_REGW = SIPexpected;
+      $display("%tns: Finished Executing Delayed SIP. Current MEPC value is %x",$time,dut.core.priv.priv.csr.csrm.MEPC_REGW);
+      RequestDelayedSIP = 0;
+    end
+  end
+ -----/\----- EXCLUDED -----/\----- */
+  
   // step 1: register expected state into the write back stage.
   always @(posedge clk) begin
     if (reset) begin
@@ -634,9 +692,12 @@ module testbench;
           case(ExpectedCSRArrayW[NumCSRPostWIndex])
             "mhartid": `checkCSR(dut.core.priv.priv.csr.csrm.MHARTID_REGW)
             "mstatus": `checkCSR(dut.core.priv.priv.csr.csrm.MSTATUS_REGW)
+            "sstatus": `checkCSR(dut.core.priv.priv.csr.csrs.SSTATUS_REGW)
             "mtvec":   `checkCSR(dut.core.priv.priv.csr.csrm.MTVEC_REGW)
             "mip":     `checkCSR(dut.core.priv.priv.csr.csrm.MIP_REGW)
             "mie":     `checkCSR(dut.core.priv.priv.csr.csrm.MIE_REGW)
+            "sip":     `checkCSR(dut.core.priv.priv.csr.csrs.SIP_REGW)
+            "sie":     `checkCSR(dut.core.priv.priv.csr.csrs.SIE_REGW)
             "mideleg": `checkCSR(dut.core.priv.priv.csr.csrm.MIDELEG_REGW)
             "medeleg": `checkCSR(dut.core.priv.priv.csr.csrm.MEDELEG_REGW)
             "mepc":    `checkCSR(dut.core.priv.priv.csr.csrm.MEPC_REGW)