mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Merge pull request #548 from davidharrishmc/dev
tlbcontrol coverage tests
This commit is contained in:
Rose Thompson
GitHub
commit
7daf8d0fbe
53
sim/wave.do
53
sim/wave.do
@ -8,11 +8,11 @@ add wave -noupdate /testbench/dut/core/SATP_REGW
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add wave -noupdate /testbench/dut/core/InstrValidM
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add wave -noupdate -expand -group HDU -group hazards /testbench/dut/core/hzu/RetM
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add wave -noupdate -expand -group HDU -group hazards -color Pink /testbench/dut/core/hzu/TrapM
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add wave -noupdate -expand -group HDU -group hazards /testbench/dut/core/hzu/LoadStallD
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add wave -noupdate -expand -group HDU -group hazards /testbench/dut/core/ieu/c/LoadStallD
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add wave -noupdate -expand -group HDU -group hazards /testbench/dut/core/ifu/IFUStallF
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add wave -noupdate -expand -group HDU -group hazards /testbench/dut/core/hzu/BPWrongE
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add wave -noupdate -expand -group HDU -group hazards /testbench/dut/core/hzu/LSUStallM
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add wave -noupdate -expand -group HDU -group hazards /testbench/dut/core/MDUStallD
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add wave -noupdate -expand -group HDU -group hazards /testbench/dut/core/ieu/c/MDUStallD
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add wave -noupdate -expand -group HDU -group hazards /testbench/dut/core/hzu/DivBusyE
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add wave -noupdate -expand -group HDU -group hazards /testbench/dut/core/hzu/FDivBusyE
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/InstrMisalignedFaultM
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@ -59,14 +59,13 @@ add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCSrcE
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add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PC1NextF
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add wave -noupdate -group {PCNext Generation} -label {NextValidPCE (from bpred)} /testbench/dut/core/ifu/NextValidPCE
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add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/CSRWriteFenceM
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add wave -noupdate -group {PCNext Generation} -expand -group pcmux3 /testbench/dut/core/priv/priv/csr/PC2NextF
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add wave -noupdate -group {PCNext Generation} -expand -group pcmux3 -group xepc /testbench/dut/core/priv/priv/csr/MEPC_REGW
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add wave -noupdate -group {PCNext Generation} -expand -group pcmux3 -group xepc /testbench/dut/core/priv/priv/csr/SEPC_REGW
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add wave -noupdate -group {PCNext Generation} -expand -group pcmux3 -group xepc /testbench/dut/core/priv/priv/csr/mretM
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add wave -noupdate -group {PCNext Generation} -expand -group pcmux3 -group xepc /testbench/dut/core/priv/priv/csr/EPC
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add wave -noupdate -group {PCNext Generation} -expand -group pcmux3 -group xepc /testbench/dut/core/priv/priv/EPCM
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add wave -noupdate -group {PCNext Generation} -expand -group pcmux3 /testbench/dut/core/priv/priv/csr/TrapVectorM
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add wave -noupdate -group {PCNext Generation} -expand -group pcmux3 /testbench/dut/core/priv/priv/csr/TrapM
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add wave -noupdate -group {PCNext Generation} -expand -group pcmux3 /testbench/dut/core/priv/priv/csr/RetM
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add wave -noupdate -group {PCNext Generation} -expand -group pcmux3 /testbench/dut/core/priv/priv/RetM
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add wave -noupdate -group {PCNext Generation} -expand -group pcmux3 /testbench/dut/core/ifu/UnalignedPCNextF
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add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCNextF
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add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCF
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@ -195,9 +194,9 @@ add wave -noupdate -group {Decode Stage} /testbench/dut/core/ifu/InstrD
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add wave -noupdate -group {Decode Stage} /testbench/InstrDName
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add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/c/InstrValidD
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add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/c/RegWriteD
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add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/dp/RdD
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add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/dp/Rs1D
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add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/dp/Rs2D
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add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/c/RdD
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add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/c/Rs1D
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add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/c/Rs2D
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add wave -noupdate -group {Execution Stage} /testbench/dut/core/ifu/PCE
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add wave -noupdate -group {Execution Stage} /testbench/dut/core/ifu/InstrE
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add wave -noupdate -group {Execution Stage} /testbench/InstrEName
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@ -251,13 +250,12 @@ add wave -noupdate -group lsu /testbench/dut/core/lsu/IEUAdrExtE
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add wave -noupdate -group lsu /testbench/dut/core/lsu/IEUAdrExtM
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add wave -noupdate -group lsu /testbench/dut/core/lsu/bus/dcache/dcache/NextSet
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add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CacheRW
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add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CMOp
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add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CMOpM
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add wave -noupdate -group lsu -expand -group dcache -color Gold /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/CurrState
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add wave -noupdate -group lsu -expand -group dcache -group SRAM-update-control /testbench/dut/core/lsu/bus/dcache/dcache/SetValid
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add wave -noupdate -group lsu -expand -group dcache -group SRAM-update-control /testbench/dut/core/lsu/bus/dcache/dcache/ClearValid
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add wave -noupdate -group lsu -expand -group dcache -group SRAM-update-control /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty
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add wave -noupdate -group lsu -expand -group dcache -group SRAM-update-control /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
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add wave -noupdate -group lsu -expand -group dcache -group SRAM-update-control /testbench/dut/core/lsu/bus/dcache/dcache/SelFlush
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add wave -noupdate -group lsu -expand -group dcache -group SRAM-update-control /testbench/dut/core/lsu/bus/dcache/dcache/SelWay
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add wave -noupdate -group lsu -expand -group dcache -group {requesting address} /testbench/dut/core/lsu/IEUAdrE
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add wave -noupdate -group lsu -expand -group dcache -group {requesting address} /testbench/dut/core/lsu/bus/dcache/dcache/PAdr
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@ -291,7 +289,6 @@ add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/
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add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWayCntEn
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add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/FlushAdrCntEn
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add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdrFlag
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add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/SelFlush
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add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/SetValid
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add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/ClearValid
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add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty
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@ -626,24 +623,24 @@ add wave -noupdate -group alu /testbench/dut/core/ieu/dp/alu/B
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add wave -noupdate -group alu /testbench/dut/core/ieu/dp/alu/ALUResult
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add wave -noupdate -group alu /testbench/dut/core/ieu/dp/alu/BALUControl
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add wave -noupdate -group alu -divider internals
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add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/Rs1D
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add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/Rs2D
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add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/Rs1E
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add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/Rs2E
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add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/RdE
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add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/RdM
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add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/RdW
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add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/MemReadE
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add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/RegWriteM
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add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/RegWriteW
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add wave -noupdate -group Forward -color Thistle /testbench/dut/core/ieu/fw/ForwardAE
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add wave -noupdate -group Forward -color Thistle /testbench/dut/core/ieu/fw/ForwardBE
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add wave -noupdate -group Forward -color Thistle /testbench/dut/core/ieu/fw/LoadStallD
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add wave -noupdate -group Forward /testbench/dut/core/ieu/c/Rs1D
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add wave -noupdate -group Forward /testbench/dut/core/ieu/c/Rs2D
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add wave -noupdate -group Forward /testbench/dut/core/ieu/c/Rs1E
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add wave -noupdate -group Forward /testbench/dut/core/ieu/c/Rs2E
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add wave -noupdate -group Forward /testbench/dut/core/ieu/c/RdE
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add wave -noupdate -group Forward /testbench/dut/core/ieu/c/RdM
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add wave -noupdate -group Forward /testbench/dut/core/ieu/c/RdW
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add wave -noupdate -group Forward /testbench/dut/core/ieu/c/MemReadE
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add wave -noupdate -group Forward /testbench/dut/core/ieu/c/RegWriteM
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add wave -noupdate -group Forward /testbench/dut/core/ieu/c/RegWriteW
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add wave -noupdate -group Forward -color Thistle /testbench/dut/core/ieu/c/ForwardAE
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add wave -noupdate -group Forward -color Thistle /testbench/dut/core/ieu/c/ForwardBE
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add wave -noupdate -group Forward -color Thistle /testbench/dut/core/ieu/c/LoadStallD
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add wave -noupdate -group Forward /testbench/dut/core/ieu/dp/IFResultM
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add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/ForwardAE
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add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/Rs1E
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add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/RdM
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add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/RdW
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add wave -noupdate -group Forward /testbench/dut/core/ieu/c/ForwardAE
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add wave -noupdate -group Forward /testbench/dut/core/ieu/c/Rs1E
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add wave -noupdate -group Forward /testbench/dut/core/ieu/c/RdM
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add wave -noupdate -group Forward /testbench/dut/core/ieu/c/RdW
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add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/ALUResultE
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add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/SrcAE
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add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/SrcBE
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@ -308,7 +308,7 @@ module lsu import cvw::*; #(parameter cvw_t P) (
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if(P.ZICBOZ_SUPPORTED) begin
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assign BusCMOZero = CMOpM[3] & ~CacheableM;
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assign CacheCMOpM = CacheableM ? CMOpM : '0;
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assign CacheCMOpM = (CacheableM & ~SelHPTW) ? CMOpM : '0;
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assign BusAtomic = AtomicM[1] & ~CacheableM;
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end else begin
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assign BusCMOZero = '0;
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@ -139,7 +139,7 @@ module hptw import cvw::*; #(parameter cvw_t P) (
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assign LeafPTE = Executable | Writable | Readable;
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assign ValidPTE = Valid & ~(Writable & ~Readable);
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assign ValidLeafPTE = ValidPTE & LeafPTE;
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assign ValidNonLeafPTE = ValidPTE & ~LeafPTE;
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assign ValidNonLeafPTE = Valid & ~LeafPTE;
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if(P.SVADU_SUPPORTED) begin : hptwwrites
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logic ReadAccess, WriteAccess;
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@ -255,13 +255,14 @@ module hptw import cvw::*; #(parameter cvw_t P) (
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end
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// Page Table Walker FSM
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// there is a bug here. Each memory access needs to be potentially flushed if the PMA/P checkers
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// *** there is a bug here (RT). Each memory access needs to be potentially flushed if the PMA/P checkers
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// generate an access fault. Specially the store on UDPATE_PTE needs to check for access violation.
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// I think the solution is to do 1 of the following
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// 1. Allow the HPTW to generate exceptions and stop walking immediately.
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// 2. If the store would generate an exception don't store to dcache but still write the TLB. When we go back
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// to LEAF then the PMA/P. Wait this does not work. The PMA/P won't be looking a the address in the table, but
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// rather than physical address of the translated instruction/data. So we must generate the exception.
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// *** DH 1/1/24 another bug: when the NAPOT bits (PTE[62:61]) are nonzero on a nonleaf PTE, the walker should make a page fault (Issue 546)
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flopenl #(.TYPE(statetype)) WalkerStateReg(clk, reset | FlushW, 1'b1, NextWalkerState, IDLE, WalkerState);
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always_comb
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case (WalkerState)
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@ -85,8 +85,7 @@ module tlbcontrol import cvw::*; #(parameter cvw_t P, ITLB = 0) (
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assign PBMemoryType = PTE_PBMT & {2{Translate & TLBHit & P.SVPBMT_SUPPORTED}};
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// check if reserved, N, or PBMT bits are malformed w in RV64
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assign BadPBMT = PTE_PBMT != 0 & (~(P.SVPBMT_SUPPORTED & ENVCFG_PBMTE) |
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{PTE_X, PTE_W, PTE_R} == 3'b000) | PTE_PBMT == 3; // PBMT must be zero if not supported or for non-leaf PTEs;
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assign BadPBMT = ((PTE_PBMT != 0) & ~(P.SVPBMT_SUPPORTED & ENVCFG_PBMTE)) | PTE_PBMT == 3; // PBMT must be zero if not supported; value of 3 is reserved
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assign BadNAPOT = PTE_N & (~P.SVNAPOT_SUPPORTED | ~NAPOT4); // N must be be 0 if CVNAPOT is not supported or not 64 KiB contiguous region
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assign BadReserved = PTE_RESERVED; // Reserved bits must be zero
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@ -94,8 +93,7 @@ module tlbcontrol import cvw::*; #(parameter cvw_t P, ITLB = 0) (
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if (ITLB == 1) begin:itlb // Instruction TLB fault checking
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// User mode may only execute user mode pages, and supervisor mode may
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// only execute non-user mode pages.
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assign ImproperPrivilege = ((EffectivePrivilegeMode == P.U_MODE) & ~PTE_U) |
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((EffectivePrivilegeMode == P.S_MODE) & PTE_U);
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assign ImproperPrivilege = ((PrivilegeModeW == P.U_MODE) & ~PTE_U) | ((PrivilegeModeW == P.S_MODE) & PTE_U);
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assign PreUpdateDA = ~PTE_A;
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assign InvalidAccess = ~PTE_X;
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end else begin:dtlb // Data TLB fault checking
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@ -44,8 +44,9 @@ string tvpaths[] = '{
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string coverage64gc[] = '{
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`COVERAGE,
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"ieu",
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"tlbmisc",
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"tlbNAPOT",
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"ieu",
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"priv",
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"ebu",
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"csrwrites",
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333
tests/coverage/tlbmisc.S
Normal file
333
tests/coverage/tlbmisc.S
Normal file
@ -0,0 +1,333 @@
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///////////////////////////////////////////
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// tlbmisc.S
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//
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// Written David_Harris@hmc.edu 1/1/24
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//
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// Purpose: Test coverage for other TLB issues
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
|
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
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//
|
||||
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
||||
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
||||
// may obtain a copy of the License at
|
||||
//
|
||||
// https://solderpad.org/licenses/SHL-2.1/
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
||||
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||
// either express or implied. See the License for the specific language governing permissions
|
||||
// and limitations under the License.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// load code to initalize stack, handle interrupts, terminate
|
||||
|
||||
#include "WALLY-init-lib.h"
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||||
|
||||
# run-elf.bash find this in project description
|
||||
main:
|
||||
li t5, 0x1
|
||||
slli t5, t5, 62
|
||||
ori t5, t5, 0xF0
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||||
csrs menvcfg, t5 # menvcfg.PBMTE = 1, CBZE, CBCFE, CBIE all 1
|
||||
|
||||
# store ret instruction in case we jump to an address mapping to 80000000
|
||||
li t0, 0x80000000
|
||||
li t5, 0x8082 # return instruction opcode
|
||||
sw t5, 0(t0)
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||||
fence.i
|
||||
|
||||
# Page table root address at 0x80010000; SV48
|
||||
li t5, 0x9000000000080010
|
||||
csrw satp, t5
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||||
|
||||
# sfence.vma x0, x0
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||||
|
||||
# switch to supervisor mode
|
||||
li a0, 1
|
||||
ecall
|
||||
|
||||
# Instruction fetch from misaligned pages
|
||||
jal changetoipfhandler # set up trap handler to return from instruction page fault if necessary
|
||||
li t0, 0x8000000000
|
||||
jalr ra, t0 # jump misaligned terapage
|
||||
li t0, 0x00000000
|
||||
jalr ra, t0 # jump to misaligned gigapage
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||||
li t0, 0x80200000
|
||||
jalr ra, t0 # jump to misaligned megapage
|
||||
|
||||
# exercise ebufsmarb
|
||||
li t0, 0x80000000
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||||
lw t1, 0(t0) # fetch from an address to warm up tlb entries
|
||||
li t0, 0x80A00000
|
||||
lw t1, 0(t0) # trigger TLB miss on a non-first entry
|
||||
jal backandforth
|
||||
|
||||
# exercise malformed PBMT pages
|
||||
|
||||
# page has PBMT = 3 (reserved)
|
||||
li t0, 0x80400000
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||||
lw t1, 0(t0) # read from page
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||||
sw t1, 0(t0) # write to page
|
||||
jalr ra, t0 # jump to page
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||||
|
||||
# Nonleaf PTE has PBMT != 0 # this should cause a page fault during page walking. However, as of issue 546 1/1/24, both ImperasDV and Wally don't detect this
|
||||
li t0, 0x80600000
|
||||
lw t1, 0(t0) # read from page
|
||||
sw t1, 0(t0) # write to page
|
||||
jalr ra, t0 # jump to page
|
||||
|
||||
|
||||
# change back to default trap handler after checking everything that might cause an instruction page fault
|
||||
jal changetodefaulthandler
|
||||
|
||||
# exercise CBOM instructions with various permissions
|
||||
li t0, 0x80800000
|
||||
cbo.zero (t0)
|
||||
cbo.clean (t0)
|
||||
li t0, 0x80801000
|
||||
cbo.zero (t0)
|
||||
cbo.clean (t0)
|
||||
li t0, 0x80802000
|
||||
cbo.zero (t0)
|
||||
cbo.clean (t0)
|
||||
li t0, 0x80803000
|
||||
cbo.zero (t0)
|
||||
cbo.clean (t0)
|
||||
li t0, 0x80804000
|
||||
cbo.zero (t0)
|
||||
cbo.clean (t0)
|
||||
|
||||
# set mstatus.MXR
|
||||
li a0, 3
|
||||
ecall
|
||||
li t0, 1
|
||||
slli t0, t0, 19
|
||||
csrs mstatus, t0 # mstatus.mxr = 1
|
||||
li a0, 1
|
||||
ecall
|
||||
|
||||
# exercise CBOM again now that MXR is set
|
||||
li t0, 0x80800000
|
||||
cbo.zero (t0)
|
||||
cbo.clean (t0)
|
||||
li t0, 0x80801000
|
||||
cbo.zero (t0)
|
||||
cbo.clean (t0)
|
||||
li t0, 0x80802000
|
||||
cbo.zero (t0)
|
||||
cbo.clean (t0)
|
||||
li t0, 0x80803000
|
||||
cbo.zero (t0)
|
||||
cbo.clean (t0)
|
||||
li t0, 0x80804000
|
||||
cbo.zero (t0)
|
||||
cbo.clean (t0)
|
||||
|
||||
# clear mstatus.MXR
|
||||
li a0, 3
|
||||
ecall
|
||||
li t0, 1
|
||||
slli t0, t0, 19
|
||||
csrc mstatus, t0 # mstatus.mxr = 1
|
||||
li a0, 1
|
||||
ecall
|
||||
|
||||
|
||||
# wrap up
|
||||
li a0, 3 # switch back to machine mode because code at 0x80000000 may not have clean page table entry
|
||||
ecall
|
||||
j done
|
||||
|
||||
backandforth:
|
||||
ret
|
||||
|
||||
changetoipfhandler:
|
||||
li a0, 3
|
||||
ecall # switch to machine mode
|
||||
la a0, ipf_handler
|
||||
csrw mtvec, a0 # point to new handler
|
||||
li a0, 1
|
||||
ecall # switch back to supervisor mode
|
||||
ret
|
||||
|
||||
changetodefaulthandler:
|
||||
li a0, 3
|
||||
ecall # switch to machine mode
|
||||
la a0, trap_handler
|
||||
csrw mtvec, a0 # point to new handler
|
||||
li a0, 1
|
||||
ecall # switch back to supervisor mode
|
||||
ret
|
||||
|
||||
instructionpagefaulthandler:
|
||||
csrw mepc, ra # go back to calling function
|
||||
mret
|
||||
|
||||
.align 4 # trap handlers must be aligned to multiple of 4
|
||||
ipf_handler:
|
||||
# Load trap handler stack pointer tp
|
||||
csrrw tp, mscratch, tp # swap MSCRATCH and tp
|
||||
sd t0, 0(tp) # Save t0 and t1 on the stack
|
||||
sd t1, -8(tp)
|
||||
csrr t0, mcause # Check the cause
|
||||
li t1, 8 # is it an ecall trap?
|
||||
andi t0, t0, 0xFC # if CAUSE = 8, 9, or 11
|
||||
beq t0, t1, ecall # yes, take ecall
|
||||
csrr t0, mcause
|
||||
li t1, 12 # is it an instruction page fault
|
||||
beq t0, t1, ipf # yes, return to calling function
|
||||
j trap_return
|
||||
|
||||
ipf:
|
||||
csrw mepc, ra # return to calling function
|
||||
ld t1, -8(tp) # restore t1 and t0
|
||||
ld t0, 0(tp)
|
||||
csrrw tp, mscratch, tp # restore tp
|
||||
mret # return from trap
|
||||
|
||||
.data
|
||||
|
||||
.align 16
|
||||
# root Page table situated at 0x80010000
|
||||
pagetable:
|
||||
.8byte 0x200044C1 # 0x00000000-0x80_00000000: PTE at 0x80011000 C1 dirty, accessed, valid
|
||||
.8byte 0x00000000000010CF # misaligned terapage at 0x80_00000000
|
||||
|
||||
# next page table at 0x80011000
|
||||
.align 12
|
||||
.8byte 0x00000000000010CF # misaligned gigapage at 0x00000000
|
||||
.8byte 0x00000000200058C1 # PTE for pages at 0x40000000
|
||||
.8byte 0x00000000200048C1 # gigapage at 0x80000000 pointing to 0x80120000
|
||||
|
||||
|
||||
# Next page table at 0x80012000 for gigapage at 0x80000000
|
||||
.align 12
|
||||
.8byte 0x0000000020004CC1 # for VA starting at 80000000 (pointer to NAPOT 64 KiB pages)
|
||||
.8byte 0x0000000020014CCF # for VA starting at 80200000 (misaligned megapage)
|
||||
.8byte 0x00000000200050C1 # for VA starting at 80400000 (bad PBMT pages)
|
||||
.8byte 0x4000000020004CC1 # for VA starting at 80600000 (bad entry: nonleaf PTE can't have PBMT != 0)
|
||||
.8byte 0x00000000200054C1 # for VA starting at 80800000 (testing rwx permissiosn with cbom/cboz)
|
||||
.8byte 0x0000000020004CC1 # for VA starting at 80A00000 (pointer to NAPOT 64 KiB pages like at 80000000)
|
||||
.8byte 0x0000000020004CC1
|
||||
.8byte 0x0000000020004CC1
|
||||
.8byte 0x0000000020004CC1
|
||||
.8byte 0x0000000020004CC1
|
||||
.8byte 0x0000000020004CC1
|
||||
.8byte 0x0000000020004CC1
|
||||
.8byte 0x0000000020004CC1
|
||||
.8byte 0x0000000020004CC1
|
||||
.8byte 0x0000000020004CC1
|
||||
.8byte 0x0000000020004CC1
|
||||
.8byte 0x0000000020004CC1
|
||||
.8byte 0x0000000020004CC1
|
||||
.8byte 0x0000000020004CC1
|
||||
.8byte 0x0000000020004CC1
|
||||
.8byte 0x0000000020004CC1
|
||||
.8byte 0x0000000020004CC1
|
||||
.8byte 0x0000000020004CC1
|
||||
.8byte 0x0000000020004CC1
|
||||
.8byte 0x0000000020004CC1
|
||||
.8byte 0x0000000020004CC1
|
||||
.8byte 0x0000000020004CC1
|
||||
.8byte 0x0000000020004CC1
|
||||
.8byte 0x0000000020004CC1
|
||||
.8byte 0x0000000020004CC1
|
||||
.8byte 0x0000000020004CC1
|
||||
.8byte 0x0000000020004CC1
|
||||
.8byte 0x0000000020004CC1
|
||||
.8byte 0x0000000020004CC1
|
||||
.8byte 0x0000000020004CC1
|
||||
.8byte 0x0000000020004CC1
|
||||
.8byte 0x0000000020004CC1
|
||||
.8byte 0x0000000020004CC1
|
||||
|
||||
# Leaf page table at 0x80013000 with NAPOT pages
|
||||
.align 12
|
||||
#80000000
|
||||
.8byte 0xA0000000200020CF
|
||||
.8byte 0xA0000000200020CF
|
||||
.8byte 0xA0000000200020CF
|
||||
.8byte 0xA0000000200020CF
|
||||
|
||||
.8byte 0xA0000000200020CF
|
||||
.8byte 0xA0000000200020CF
|
||||
.8byte 0xA0000000200020CF
|
||||
.8byte 0xA0000000200020CF
|
||||
|
||||
.8byte 0xA0000000200020CF
|
||||
.8byte 0xA0000000200020CF
|
||||
.8byte 0xA0000000200020CF
|
||||
.8byte 0xA0000000200020CF
|
||||
|
||||
.8byte 0xA0000000200020CF
|
||||
.8byte 0xA0000000200020CF
|
||||
.8byte 0xA0000000200020CF
|
||||
.8byte 0xA0000000200020CF
|
||||
|
||||
.8byte 0x80000000200060CF
|
||||
.8byte 0x80000000200060CF
|
||||
.8byte 0x80000000200060CF
|
||||
.8byte 0x80000000200060CF
|
||||
|
||||
.8byte 0x80000000200060CF
|
||||
.8byte 0x80000000200060CF
|
||||
.8byte 0x80000000200060CF
|
||||
.8byte 0x80000000200060CF
|
||||
|
||||
.8byte 0x80000000200060CF
|
||||
.8byte 0x80000000200060CF
|
||||
.8byte 0x80000000200060CF
|
||||
.8byte 0x80000000200060CF
|
||||
|
||||
.8byte 0x80000000200060CF
|
||||
.8byte 0x80000000200060CF
|
||||
.8byte 0x80000000200060CF
|
||||
.8byte 0x80000000200060CF
|
||||
|
||||
.8byte 0x800000002000A0CF
|
||||
.8byte 0x800000002000A0CF
|
||||
.8byte 0x800000002000A0CF
|
||||
.8byte 0x800000002000A0CF
|
||||
|
||||
.8byte 0x800000002000A0CF
|
||||
.8byte 0x800000002000A0CF
|
||||
.8byte 0x800000002000A0CF
|
||||
.8byte 0x800000002000A0CF
|
||||
|
||||
.8byte 0x800000002000A0CF
|
||||
.8byte 0x800000002000A0CF
|
||||
.8byte 0x800000002000A0CF
|
||||
.8byte 0x800000002000A0CF
|
||||
|
||||
.8byte 0x800000002000A0CF
|
||||
.8byte 0x800000002000A0CF
|
||||
.8byte 0x800000002000A0CF
|
||||
.8byte 0x800000002000A0CF
|
||||
|
||||
.8byte 0x800000002000E0CF
|
||||
.8byte 0x800000002000E0CF
|
||||
.8byte 0x800000002000E0CF
|
||||
.8byte 0x800000002000E0CF
|
||||
|
||||
.8byte 0x800000002000E0CF
|
||||
.8byte 0x800000002000E0CF
|
||||
|
||||
# Leaf page table at 0x80014000 with PBMT pages
|
||||
.align 12
|
||||
#80400000
|
||||
.8byte 0x60000000200020CF # reserved entry
|
||||
|
||||
# Leaf page table at 0x80015000 with various permissions for testing CBOM and CBOZ
|
||||
.align 12
|
||||
#80800000
|
||||
.8byte 0x00000000200000CF # valid rwx for VA 80800000
|
||||
.8byte 0x00000000200000CB # valid r x for VA 80801000
|
||||
.8byte 0x00000000200000C3 # valid r for VA 80802000
|
||||
.8byte 0x00000000200000C5 # valid x for VA 80803000
|
||||
.8byte 0x00000000200000CD # valid wx for VA 80804000 (illegal combination, but used to test tlbcontrol)
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user