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https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
added support to due partial fpga simulation.
This commit is contained in:
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4d1b02c068
commit
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@ -1,5 +1,5 @@
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#PERIOD = 22000000
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PERIOD = 22000000
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PERIOD = 20
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#PERIOD = 20
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.section .init
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.section .init
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.global _start
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.global _start
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@ -139,7 +139,8 @@ module SDC
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// currently does not support writes
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// currently does not support writes
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assign InitTrans = HREADY & HSELSDC & (HTRANS != 2'b00);
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assign InitTrans = HREADY & HSELSDC & (HTRANS != 2'b00);
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assign RegRead = InitTrans & ~HWRITE;
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//assign RegRead = InitTrans & ~HWRITE;
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flopr #(1) RegReadReg(HCLK, ~HRESETn, InitTrans & ~HWRITE, RegRead);
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// AHBLite Spec has write data 1 cycle after write command
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// AHBLite Spec has write data 1 cycle after write command
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flopr #(1) RegWriteReg(HCLK, ~HRESETn, InitTrans & HWRITE, RegWrite);
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flopr #(1) RegWriteReg(HCLK, ~HRESETn, InitTrans & HWRITE, RegWrite);
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@ -256,7 +257,7 @@ module SDC
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end else if (Command[2] | Command[1]) begin
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end else if (Command[2] | Command[1]) begin
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NextState = STATE_PROCESS_CMD;
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NextState = STATE_PROCESS_CMD;
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HREADYSDC = 1'b0;
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HREADYSDC = 1'b0;
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end else if(HADDR[4:0] == 'h18 & RegRead) begin
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end else if(HADDRDelay[4:0] == 'h18 & RegRead) begin
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NextState = STATE_READ;
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NextState = STATE_READ;
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HREADYSDC = 1'b0;
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HREADYSDC = 1'b0;
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end else begin
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end else begin
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@ -53,7 +53,7 @@ module dtim #(parameter BASE=0, RANGE = 65535, string PRELOAD="") (
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initial begin
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initial begin
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//$readmemh(PRELOAD, RAM);
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//$readmemh(PRELOAD, RAM);
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RAM[0] = 64'h8c61819300002197;
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RAM[0] = 64'h9441819300002197;
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RAM[1] = 64'h4281420141014081;
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RAM[1] = 64'h4281420141014081;
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RAM[2] = 64'h4481440143814301;
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RAM[2] = 64'h4481440143814301;
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RAM[3] = 64'h4681460145814501;
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RAM[3] = 64'h4681460145814501;
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@ -61,23 +61,39 @@ module dtim #(parameter BASE=0, RANGE = 65535, string PRELOAD="") (
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RAM[5] = 64'h4a814a0149814901;
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RAM[5] = 64'h4a814a0149814901;
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RAM[6] = 64'h4c814c014b814b01;
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RAM[6] = 64'h4c814c014b814b01;
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RAM[7] = 64'h4e814e014d814d01;
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RAM[7] = 64'h4e814e014d814d01;
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RAM[8] = 64'h0ff001134f814f01;
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RAM[8] = 64'h0110011b4f814f01;
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RAM[9] = 64'h00818213100121b7;
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RAM[9] = 64'h059b45011161016e;
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RAM[10] = 64'h0022a02300c18293;
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RAM[10] = 64'h0800063705fe0010;
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RAM[11] = 64'h6bc14a8100222023;
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RAM[11] = 64'h0ff00393056000ef;
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RAM[12] = 64'h4c010b7e00100b1b;
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RAM[12] = 64'h4e952e3110012e37;
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RAM[13] = 64'h018ca023018b0cb3;
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RAM[13] = 64'h8c02829b00a7e2b7;
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RAM[14] = 64'h4c01ff7c4be30c11;
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RAM[14] = 64'h2023fe02dfe312fd;
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RAM[15] = 64'h000caa83018b0cb3;
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RAM[15] = 64'h829b00a7e2b7007e;
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RAM[16] = 64'h49e30c11038a9063;
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RAM[16] = 64'hfe02dfe312fd8c02;
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RAM[17] = 64'h0a1b014fba37ff7c;
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RAM[17] = 64'h4de31efd000e2023;
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RAM[18] = 64'hfe0a5fe31a7d180a;
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RAM[18] = 64'h059bf1402573fdd0;
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RAM[19] = 64'hb7f50022a0230105;
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RAM[19] = 64'h0000061705e20870;
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RAM[20] = 64'h8e0a0a1b0010da37;
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RAM[20] = 64'h0010029b01260613;
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RAM[21] = 64'ha023fe0a5fe31a7d;
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RAM[21] = 64'h11010002806702fe;
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RAM[22] = 64'h0a1b0010da370002;
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RAM[22] = 64'h84b2842ae426e822;
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RAM[23] = 64'hfe0a5fe31a7d8e0a;
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RAM[23] = 64'h892ee04aec064505;
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RAM[24] = 64'h0000bff10022a023;
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RAM[24] = 64'h06c000ef07c000ef;
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RAM[25] = 64'h979334fd02905463;
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RAM[26] = 64'h07930177d4930204;
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RAM[27] = 64'h94be200909132004;
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RAM[28] = 64'h2004041385ca8522;
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RAM[29] = 64'hfe941ae3014000ef;
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RAM[30] = 64'h690264a2644260e2;
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RAM[31] = 64'h2783674980826105;
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RAM[32] = 64'h3823dfed8b851047;
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RAM[33] = 64'h10f72423479110a7;
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RAM[34] = 64'h8b89104727836749;
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RAM[35] = 64'h674920058693ffed;
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RAM[36] = 64'hbc2305a111873783;
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RAM[37] = 64'h8082fed59be3fef5;
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RAM[38] = 64'h8b85104727836749;
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RAM[39] = 64'ha02367c98082dfed;
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RAM[40] = 64'h00000000808210a7;
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end
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end
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41
wally-pipelined/src/wally/ila_0.sv
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41
wally-pipelined/src/wally/ila_0.sv
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@ -0,0 +1,41 @@
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///////////////////////////////////////////
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// ila_0.sv
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//
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// Written: Ross Thompson September 26, 2021
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// Modified:
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//
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// Purpose: stub for simulation. does nothing.
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
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// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
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// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
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// is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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///////////////////////////////////////////
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`include "wally-config.vh"
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module ila_0
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(input logic clk,
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input logic [`XLEN-1:0] probe0,
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input logic [`XLEN-1:0] probe1,
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input logic [`XLEN-1:0] probe2,
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input logic [`XLEN-1:0] probe3,
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input logic probe4,
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input logic [1:0] probe5,
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input logic [31:0] probe6
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);
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endmodule; // ila_0
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@ -503,7 +503,9 @@ string tests32f[] = '{
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string tests[];
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string tests[];
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string ProgramAddrMapFile, ProgramLabelMapFile;
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string ProgramAddrMapFile, ProgramLabelMapFile;
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logic [`AHBW-1:0] HRDATAEXT;
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logic [`AHBW-1:0] HRDATAEXT;
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logic HREADYEXT, HRESPEXT;
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logic HREADYEXT, HRESPEXT, HREADY;
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logic HSELEXT;
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logic [31:0] HADDR;
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logic [31:0] HADDR;
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logic [`AHBW-1:0] HWDATA;
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logic [`AHBW-1:0] HWDATA;
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logic HWRITE;
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logic HWRITE;
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@ -581,9 +583,13 @@ string tests32f[] = '{
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// instantiate device to be tested
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// instantiate device to be tested
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assign GPIOPinsIn = 0;
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assign GPIOPinsIn = 0;
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assign UARTSin = 1;
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assign UARTSin = 1;
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assign HREADYEXT = 1;
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assign HRESPEXT = 0;
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dtim #(.BASE(`TIM_BASE), .RANGE(`TIM_RANGE))
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assign HRDATAEXT = 0;
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dtim (.*, .HSELTim(HSELEXT),
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.HREADTim(HRDATAEXT),
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.HREADYTim(HREADYEXT),
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.HRESPTim(HRESPEXT));
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wallypipelinedsoc dut(.*);
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wallypipelinedsoc dut(.*);
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@ -615,7 +621,7 @@ string tests32f[] = '{
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/* -----\/----- EXCLUDED -----\/-----
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/* -----\/----- EXCLUDED -----\/-----
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if (`TESTSBP) begin
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if (`TESTSBP) begin
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for (i=MemStartAddr; i<MemEndAddr; i = i+1) begin
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for (i=MemStartAddr; i<MemEndAddr; i = i+1) begin
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dut.uncore.dtim.RAM[i] = meminit;
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dtim.RAM[i] = meminit;
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end
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end
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end
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end
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-----/\----- EXCLUDED -----/\----- */
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-----/\----- EXCLUDED -----/\----- */
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@ -623,7 +629,7 @@ string tests32f[] = '{
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memfilename = {"../../imperas-riscv-tests/work/", tests[test], ".elf.memfile"};
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memfilename = {"../../imperas-riscv-tests/work/", tests[test], ".elf.memfile"};
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romfilename = {"../../imperas-riscv-tests/work/rv64BP/fpga-test-sdc.memfile"};
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romfilename = {"../../imperas-riscv-tests/work/rv64BP/fpga-test-sdc.memfile"};
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sdcfilename = {"../src/sdc/tb/ramdisk2.hex"};
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sdcfilename = {"../src/sdc/tb/ramdisk2.hex"};
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$readmemh(memfilename, dut.uncore.dtim.RAM);
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$readmemh(memfilename, dtim.RAM);
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$readmemh(romfilename, dut.uncore.bootdtim.bootdtim.RAM);
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$readmemh(romfilename, dut.uncore.bootdtim.bootdtim.RAM);
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$readmemh(sdcfilename, sdcard.FLASHmem);
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$readmemh(sdcfilename, sdcard.FLASHmem);
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ProgramAddrMapFile = {"../../imperas-riscv-tests/work/rv64BP/fpga-test-sdc.objdump.addr"};
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ProgramAddrMapFile = {"../../imperas-riscv-tests/work/rv64BP/fpga-test-sdc.objdump.addr"};
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@ -684,14 +690,14 @@ string tests32f[] = '{
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/* verilator lint_off INFINITELOOP */
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/* verilator lint_off INFINITELOOP */
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while (signature[i] !== 'bx) begin
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while (signature[i] !== 'bx) begin
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//$display("signature[%h] = %h", i, signature[i]);
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//$display("signature[%h] = %h", i, signature[i]);
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if (signature[i] !== dut.uncore.dtim.RAM[testadr+i] &&
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if (signature[i] !== dtim.RAM[testadr+i] &&
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(signature[i] !== DCacheFlushFSM.ShadowRAM[testadr+i])) begin
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(signature[i] !== DCacheFlushFSM.ShadowRAM[testadr+i])) begin
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if (signature[i+4] !== 'bx || signature[i] !== 32'hFFFFFFFF) begin
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if (signature[i+4] !== 'bx || signature[i] !== 32'hFFFFFFFF) begin
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// report errors unless they are garbage at the end of the sim
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// report errors unless they are garbage at the end of the sim
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// kind of hacky test for garbage right now
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// kind of hacky test for garbage right now
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errors = errors+1;
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errors = errors+1;
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$display(" Error on test %s result %d: adr = %h sim (D$) %h sim (TIM) = %h, signature = %h",
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$display(" Error on test %s result %d: adr = %h sim (D$) %h sim (TIM) = %h, signature = %h",
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tests[test], i, (testadr+i)*(`XLEN/8), DCacheFlushFSM.ShadowRAM[testadr+i], dut.uncore.dtim.RAM[testadr+i], signature[i]);
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tests[test], i, (testadr+i)*(`XLEN/8), DCacheFlushFSM.ShadowRAM[testadr+i], dtim.RAM[testadr+i], signature[i]);
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$stop;//***debug
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$stop;//***debug
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end
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end
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end
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end
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@ -713,7 +719,7 @@ string tests32f[] = '{
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end
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end
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else begin
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else begin
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memfilename = {"../../imperas-riscv-tests/work/", tests[test], ".elf.memfile"};
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memfilename = {"../../imperas-riscv-tests/work/", tests[test], ".elf.memfile"};
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$readmemh(memfilename, dut.uncore.dtim.RAM);
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$readmemh(memfilename, dtim.RAM);
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$display("Read memfile %s", memfilename);
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$display("Read memfile %s", memfilename);
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ProgramAddrMapFile = {"../../imperas-riscv-tests/work/", tests[test], ".elf.objdump.addr"};
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ProgramAddrMapFile = {"../../imperas-riscv-tests/work/", tests[test], ".elf.objdump.addr"};
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ProgramLabelMapFile = {"../../imperas-riscv-tests/work/", tests[test], ".elf.objdump.lab"};
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ProgramLabelMapFile = {"../../imperas-riscv-tests/work/", tests[test], ".elf.objdump.lab"};
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