From 7d749b201b9a3e6128a45e923bffbc34dc3d9a94 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Sun, 26 Sep 2021 15:00:00 -0500 Subject: [PATCH] added support to due partial fpga simulation. --- testsBP/fpga-test-sdc/bios.s | 4 +- wally-pipelined/src/sdc/SDC.sv | 5 +- wally-pipelined/src/uncore/dtim.sv | 66 +++++++++++++-------- wally-pipelined/src/wally/ila_0.sv | 41 +++++++++++++ wally-pipelined/testbench/testbench-fpga.sv | 24 +++++--- 5 files changed, 102 insertions(+), 38 deletions(-) create mode 100644 wally-pipelined/src/wally/ila_0.sv diff --git a/testsBP/fpga-test-sdc/bios.s b/testsBP/fpga-test-sdc/bios.s index e8e23fc8f..8c37dceed 100644 --- a/testsBP/fpga-test-sdc/bios.s +++ b/testsBP/fpga-test-sdc/bios.s @@ -1,5 +1,5 @@ -#PERIOD = 22000000 -PERIOD = 20 +PERIOD = 22000000 +#PERIOD = 20 .section .init .global _start diff --git a/wally-pipelined/src/sdc/SDC.sv b/wally-pipelined/src/sdc/SDC.sv index 90865466b..3ad5abfb9 100644 --- a/wally-pipelined/src/sdc/SDC.sv +++ b/wally-pipelined/src/sdc/SDC.sv @@ -139,7 +139,8 @@ module SDC // currently does not support writes assign InitTrans = HREADY & HSELSDC & (HTRANS != 2'b00); - assign RegRead = InitTrans & ~HWRITE; + //assign RegRead = InitTrans & ~HWRITE; + flopr #(1) RegReadReg(HCLK, ~HRESETn, InitTrans & ~HWRITE, RegRead); // AHBLite Spec has write data 1 cycle after write command flopr #(1) RegWriteReg(HCLK, ~HRESETn, InitTrans & HWRITE, RegWrite); @@ -256,7 +257,7 @@ module SDC end else if (Command[2] | Command[1]) begin NextState = STATE_PROCESS_CMD; HREADYSDC = 1'b0; - end else if(HADDR[4:0] == 'h18 & RegRead) begin + end else if(HADDRDelay[4:0] == 'h18 & RegRead) begin NextState = STATE_READ; HREADYSDC = 1'b0; end else begin diff --git a/wally-pipelined/src/uncore/dtim.sv b/wally-pipelined/src/uncore/dtim.sv index f0e123beb..4c2d75cba 100644 --- a/wally-pipelined/src/uncore/dtim.sv +++ b/wally-pipelined/src/uncore/dtim.sv @@ -53,31 +53,47 @@ module dtim #(parameter BASE=0, RANGE = 65535, string PRELOAD="") ( initial begin //$readmemh(PRELOAD, RAM); - RAM[0] = 64'h8c61819300002197; - RAM[1] = 64'h4281420141014081; - RAM[2] = 64'h4481440143814301; - RAM[3] = 64'h4681460145814501; - RAM[4] = 64'h4881480147814701; - RAM[5] = 64'h4a814a0149814901; - RAM[6] = 64'h4c814c014b814b01; - RAM[7] = 64'h4e814e014d814d01; - RAM[8] = 64'h0ff001134f814f01; - RAM[9] = 64'h00818213100121b7; - RAM[10] = 64'h0022a02300c18293; - RAM[11] = 64'h6bc14a8100222023; - RAM[12] = 64'h4c010b7e00100b1b; - RAM[13] = 64'h018ca023018b0cb3; - RAM[14] = 64'h4c01ff7c4be30c11; - RAM[15] = 64'h000caa83018b0cb3; - RAM[16] = 64'h49e30c11038a9063; - RAM[17] = 64'h0a1b014fba37ff7c; - RAM[18] = 64'hfe0a5fe31a7d180a; - RAM[19] = 64'hb7f50022a0230105; - RAM[20] = 64'h8e0a0a1b0010da37; - RAM[21] = 64'ha023fe0a5fe31a7d; - RAM[22] = 64'h0a1b0010da370002; - RAM[23] = 64'hfe0a5fe31a7d8e0a; - RAM[24] = 64'h0000bff10022a023; + RAM[0] = 64'h9441819300002197; + RAM[1] = 64'h4281420141014081; + RAM[2] = 64'h4481440143814301; + RAM[3] = 64'h4681460145814501; + RAM[4] = 64'h4881480147814701; + RAM[5] = 64'h4a814a0149814901; + RAM[6] = 64'h4c814c014b814b01; + RAM[7] = 64'h4e814e014d814d01; + RAM[8] = 64'h0110011b4f814f01; + RAM[9] = 64'h059b45011161016e; + RAM[10] = 64'h0800063705fe0010; + RAM[11] = 64'h0ff00393056000ef; + RAM[12] = 64'h4e952e3110012e37; + RAM[13] = 64'h8c02829b00a7e2b7; + RAM[14] = 64'h2023fe02dfe312fd; + RAM[15] = 64'h829b00a7e2b7007e; + RAM[16] = 64'hfe02dfe312fd8c02; + RAM[17] = 64'h4de31efd000e2023; + RAM[18] = 64'h059bf1402573fdd0; + RAM[19] = 64'h0000061705e20870; + RAM[20] = 64'h0010029b01260613; + RAM[21] = 64'h11010002806702fe; + RAM[22] = 64'h84b2842ae426e822; + RAM[23] = 64'h892ee04aec064505; + RAM[24] = 64'h06c000ef07c000ef; + RAM[25] = 64'h979334fd02905463; + RAM[26] = 64'h07930177d4930204; + RAM[27] = 64'h94be200909132004; + RAM[28] = 64'h2004041385ca8522; + RAM[29] = 64'hfe941ae3014000ef; + RAM[30] = 64'h690264a2644260e2; + RAM[31] = 64'h2783674980826105; + RAM[32] = 64'h3823dfed8b851047; + RAM[33] = 64'h10f72423479110a7; + RAM[34] = 64'h8b89104727836749; + RAM[35] = 64'h674920058693ffed; + RAM[36] = 64'hbc2305a111873783; + RAM[37] = 64'h8082fed59be3fef5; + RAM[38] = 64'h8b85104727836749; + RAM[39] = 64'ha02367c98082dfed; + RAM[40] = 64'h00000000808210a7; end diff --git a/wally-pipelined/src/wally/ila_0.sv b/wally-pipelined/src/wally/ila_0.sv new file mode 100644 index 000000000..1a78b9af8 --- /dev/null +++ b/wally-pipelined/src/wally/ila_0.sv @@ -0,0 +1,41 @@ +/////////////////////////////////////////// +// ila_0.sv +// +// Written: Ross Thompson September 26, 2021 +// Modified: +// +// Purpose: stub for simulation. does nothing. +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + + +`include "wally-config.vh" + +module ila_0 + (input logic clk, + input logic [`XLEN-1:0] probe0, + input logic [`XLEN-1:0] probe1, + input logic [`XLEN-1:0] probe2, + input logic [`XLEN-1:0] probe3, + input logic probe4, + input logic [1:0] probe5, + input logic [31:0] probe6 + ); +endmodule; // ila_0 + + diff --git a/wally-pipelined/testbench/testbench-fpga.sv b/wally-pipelined/testbench/testbench-fpga.sv index f7c804121..13671f68b 100644 --- a/wally-pipelined/testbench/testbench-fpga.sv +++ b/wally-pipelined/testbench/testbench-fpga.sv @@ -503,7 +503,9 @@ string tests32f[] = '{ string tests[]; string ProgramAddrMapFile, ProgramLabelMapFile; logic [`AHBW-1:0] HRDATAEXT; - logic HREADYEXT, HRESPEXT; + logic HREADYEXT, HRESPEXT, HREADY; + logic HSELEXT; + logic [31:0] HADDR; logic [`AHBW-1:0] HWDATA; logic HWRITE; @@ -581,9 +583,13 @@ string tests32f[] = '{ // instantiate device to be tested assign GPIOPinsIn = 0; assign UARTSin = 1; - assign HREADYEXT = 1; - assign HRESPEXT = 0; - assign HRDATAEXT = 0; + + dtim #(.BASE(`TIM_BASE), .RANGE(`TIM_RANGE)) + dtim (.*, .HSELTim(HSELEXT), + .HREADTim(HRDATAEXT), + .HREADYTim(HREADYEXT), + .HRESPTim(HRESPEXT)); + wallypipelinedsoc dut(.*); @@ -615,7 +621,7 @@ string tests32f[] = '{ /* -----\/----- EXCLUDED -----\/----- if (`TESTSBP) begin for (i=MemStartAddr; i