From 7b7e87bd0b7289680123a24c349265cb44143d71 Mon Sep 17 00:00:00 2001 From: Noah Boorstin Date: Tue, 23 Feb 2021 22:01:23 +0000 Subject: [PATCH] busybear: start adding ram --- wally-pipelined/regression/wally-busybear.do | 2 + .../testbench/testbench-busybear.sv | 56 ++++++++++++++----- 2 files changed, 45 insertions(+), 13 deletions(-) diff --git a/wally-pipelined/regression/wally-busybear.do b/wally-pipelined/regression/wally-busybear.do index a6b50c23f..cd9225d77 100644 --- a/wally-pipelined/regression/wally-busybear.do +++ b/wally-pipelined/regression/wally-busybear.do @@ -48,6 +48,8 @@ add wave /testbench_busybear/lastInstrF add wave /testbench_busybear/speculative add wave /testbench_busybear/lastPC2 add wave -divider +add wave -hex /testbench_busybear/readPC +add wave -hex /testbench_busybear/readRAM #add wave -hex /testbench_busybear/dut/hart/priv/csr/MTVEC_REG #add wave -hex /testbench_busybear/dut/hart/priv/csr/MSTATUS_REG #add wave -hex /testbench_busybear/dut/hart/priv/csr/SCOUNTEREN_REG diff --git a/wally-pipelined/testbench/testbench-busybear.sv b/wally-pipelined/testbench/testbench-busybear.sv index 1b34a1fc5..13a7b2211 100644 --- a/wally-pipelined/testbench/testbench-busybear.sv +++ b/wally-pipelined/testbench/testbench-busybear.sv @@ -140,18 +140,18 @@ module testbench_busybear(); if ($time == 0) begin scan_file_rf = $fscanf(data_file_rf, "%x\n", regExpected); if (dut.hart.ieu.dp.regf.rf[i] != regExpected) begin - $display("%t ps, instr %0d: rf[%0d] does not equal rf expected: %x, %x", $time, instrs, i, dut.hart.ieu.dp.regf.rf[i], regExpected); + $display("%0t ps, instr %0d: rf[%0d] does not equal rf expected: %x, %x", $time, instrs, i, dut.hart.ieu.dp.regf.rf[i], regExpected); `ERROR end end else begin scan_file_rf = $fscanf(data_file_rf, "%d\n", regNumExpected); scan_file_rf = $fscanf(data_file_rf, "%x\n", regExpected); if (i != regNumExpected) begin - $display("%t ps, instr %0d: wrong register changed: %0d, %0d expected", $time, instrs, i, regNumExpected); + $display("%0t ps, instr %0d: wrong register changed: %0d, %0d expected", $time, instrs, i, regNumExpected); `ERROR end if (~equal(dut.hart.ieu.dp.regf.rf[i],regExpected, 0)) begin - $display("%t ps, instr %0d: rf[%0d] does not equal rf expected: %x, %x", $time, instrs, i, dut.hart.ieu.dp.regf.rf[i], regExpected); + $display("%0t ps, instr %0d: rf[%0d] does not equal rf expected: %x, %x", $time, instrs, i, dut.hart.ieu.dp.regf.rf[i], regExpected); `ERROR end if (dut.hart.ieu.dp.regf.rf[i] !== regExpected) begin @@ -162,6 +162,27 @@ module testbench_busybear(); end end endgenerate + + `define MAX_RAM 'h8000000 + logic [`XLEN-1:0] RAM[`MAX_RAM:0]; + logic [`XLEN-1:0] readRAM, readPC; + integer RAMAdr, RAMPC; + assign RAMAdr = HADDR - 'h80000000; + assign RAMPC = PCF - 'h80000000; + always @(HWDATA or HADDR or HSIZE or HWRITE or dut.hart.MemRWM[1]) begin + if ((HWRITE || dut.hart.MemRWM[1]) && (HADDR >= 'h80000000 && HADDR <= 'h87FFFFFF)) begin + if (HWRITE) begin + RAM[RAMAdr] = HWDATA; + end else begin + readRAM = RAM[RAMAdr]; + end + end + end + always @(PCF) begin + if (PCF >= 'h80000000 && PCF <= 'h87FFFFFF) begin + readPC = RAM[RAMPC]; + end + end logic [`XLEN-1:0] readAdrExpected; // this might need to change @@ -175,7 +196,12 @@ module testbench_busybear(); scan_file_memR = $fscanf(data_file_memR, "%x\n", HRDATA); #1; if (~equal(HADDR,readAdrExpected,4)) begin - $display("%t ps, instr %0d: HADDR does not equal readAdrExpected: %x, %x", $time, instrs, HADDR, readAdrExpected); + $display("%0t ps, instr %0d: HADDR does not equal readAdrExpected: %x, %x", $time, instrs, HADDR, readAdrExpected); + `ERROR + end + if (HRDATA != readRAM && (HADDR >= 'h80000000 && HADDR <= 'h87FFFFFF)) begin + $display("warning %0t ps, instr %0d: HRDATA does not equal readRAM: %x, %x from address %x", $time, instrs, HRDATA, readRAM, HADDR); + warningCount += 1; `ERROR end end @@ -183,7 +209,7 @@ module testbench_busybear(); logic [`XLEN-1:0] writeDataExpected, writeAdrExpected; // this might need to change - always @(HWDATA or HADDR or HSIZE) begin + always @(HWDATA or HADDR or HSIZE or HWRITE) begin #1; if (HWRITE) begin if($feof(data_file_memW)) begin @@ -193,11 +219,11 @@ module testbench_busybear(); scan_file_memW = $fscanf(data_file_memW, "%x\n", writeDataExpected); scan_file_memW = $fscanf(data_file_memW, "%x\n", writeAdrExpected); if (writeDataExpected != HWDATA) begin - $display("%t ps, instr %0d: HWDATA does not equal writeDataExpected: %x, %x", $time, instrs, HWDATA, writeDataExpected); + $display("%0t ps, instr %0d: HWDATA does not equal writeDataExpected: %x, %x", $time, instrs, HWDATA, writeDataExpected); `ERROR end if (~equal(writeAdrExpected,HADDR,1)) begin - $display("%t ps, instr %0d: HADDR does not equal writeAdrExpected: %x, %x", $time, instrs, HADDR, writeAdrExpected); + $display("%0t ps, instr %0d: HADDR does not equal writeAdrExpected: %x, %x", $time, instrs, HADDR, writeAdrExpected); `ERROR end end @@ -226,17 +252,17 @@ module testbench_busybear(); scan_file_csr = $fscanf(data_file_csr, "%s\n", CSR); \ scan_file_csr = $fscanf(data_file_csr, "%x\n", expected``CSR``); \ if(CSR.icompare(`"CSR`")) begin \ - $display("%t ps, instr %0d: %s changed, expected %s", $time, instrs, `"CSR`", CSR); \ + $display("%0t ps, instr %0d: %s changed, expected %s", $time, instrs, `"CSR`", CSR); \ end \ if(``PATH``.``CSR``_REGW != ``expected``CSR) begin \ - $display("%t ps, instr %0d: %s does not equal %s expected: %x, %x", $time, instrs, `"CSR`", CSR, ``PATH``.``CSR``_REGW, ``expected``CSR); \ + $display("%0t ps, instr %0d: %s does not equal %s expected: %x, %x", $time, instrs, `"CSR`", CSR, ``PATH``.``CSR``_REGW, ``expected``CSR); \ `ERROR \ end \ end else begin \ for(integer j=0; j