mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-02 17:55:19 +00:00
Update scripts/synth.tcl to add with parameter for width and also checks wrapper to see if running CONFIG=rv32e to run without WIDTH
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parent
65e536e401
commit
7b79d8edeb
@ -20,11 +20,11 @@ export MAXCORES ?= 1
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export MAXOPT ?= 0
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export MAXOPT ?= 0
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export DRIVE ?= FLOP
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export DRIVE ?= FLOP
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export USESRAM ?= 0
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export USESRAM ?= 0
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export WIDTH ?= 32
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time := $(shell date +%F-%H-%M)
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time := $(shell date +%F-%H-%M)
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hash := $(shell git rev-parse --short HEAD)
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hash := $(shell git rev-parse --short HEAD)
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export OUTPUTDIR := runs/$(DESIGN)_$(CONFIG)_$(MOD)_$(TECH)nm_$(FREQ)_MHz_$(time)_$(TITLE)_$(hash)
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export OUTPUTDIR := runs/$(DESIGN)_$(WIDTH)_$(CONFIG)_$(MOD)_$(TECH)_$(FREQ)_MHz_$(time)_$(TITLE)_$(hash)
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export SAIFPOWER ?= 0
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export SAIFPOWER ?= 0
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OLDCONFIGDIR ?= ${WALLY}/config
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OLDCONFIGDIR ?= ${WALLY}/config
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@ -147,4 +147,4 @@ clean:
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rm -f power.saif
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rm -f power.saif
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rm -f Synopsys_stack_trace_*.txt
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rm -f Synopsys_stack_trace_*.txt
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rm -f crte_*.txt
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rm -f crte_*.txt
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@ -18,7 +18,6 @@ suppress_message {VER-274}
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# Enable Multicore
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# Enable Multicore
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set_host_options -max_cores $::env(MAXCORES)
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set_host_options -max_cores $::env(MAXCORES)
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# get outputDir and configDir from environment (Makefile)
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# get outputDir and configDir from environment (Makefile)
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set outputDir $::env(OUTPUTDIR)
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set outputDir $::env(OUTPUTDIR)
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set cfg $::env(CONFIGDIR)
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set cfg $::env(CONFIGDIR)
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@ -26,6 +25,7 @@ set hdl_src "../src"
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set saifpower $::env(SAIFPOWER)
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set saifpower $::env(SAIFPOWER)
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set maxopt $::env(MAXOPT)
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set maxopt $::env(MAXOPT)
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set drive $::env(DRIVE)
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set drive $::env(DRIVE)
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set width $::env(WIDTH)
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eval file copy -force [glob ${cfg}/*.vh] {$outputDir/hdl/}
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eval file copy -force [glob ${cfg}/*.vh] {$outputDir/hdl/}
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eval file copy -force [glob ${hdl_src}/cvw.sv] {$outputDir/hdl/}
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eval file copy -force [glob ${hdl_src}/cvw.sv] {$outputDir/hdl/}
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@ -88,7 +88,13 @@ if { [shell_is_in_topographical_mode] } {
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#set alib_library_analysis_path ./$outputDir
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#set alib_library_analysis_path ./$outputDir
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define_design_lib WORK -path ./$outputDir/WORK
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define_design_lib WORK -path ./$outputDir/WORK
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analyze -f sverilog -lib WORK $my_verilog_files
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analyze -f sverilog -lib WORK $my_verilog_files
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elaborate $my_toplevel -lib WORK
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# If wrapper=0, we want to run against a specific module and pass
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# width to DC
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if { $wrapper == 1 } {
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elaborate $my_toplevel -lib WORK
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} else {
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elaborate $my_toplevel -lib WORK -parameters WIDTH=$width
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}
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# Set the current_design
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# Set the current_design
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current_design $my_toplevel
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current_design $my_toplevel
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@ -308,6 +314,8 @@ set filename [format "%s%s" $outputDir "/reports/mindelay.rep"]
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redirect $filename { report_timing -capacitance -transition_time -nets -delay_type min -nworst 1 }
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redirect $filename { report_timing -capacitance -transition_time -nets -delay_type min -nworst 1 }
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set filename [format "%s%s" $outputDir "/reports/per_module_timing.rep"]
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set filename [format "%s%s" $outputDir "/reports/per_module_timing.rep"]
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redirect -append $filename { echo "\n\n\n//// Critical paths through Stall ////\n\n\n" }
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redirect -append $filename { report_timing -capacitance -transition_time -nets -through {Stall*} -nworst 1 }
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redirect -append $filename { echo "\n\n\n//// Critical paths through ifu ////\n\n\n" }
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redirect -append $filename { echo "\n\n\n//// Critical paths through ifu ////\n\n\n" }
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redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ifu/*} -nworst 1 }
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redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ifu/*} -nworst 1 }
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redirect -append $filename { echo "\n\n\n//// Critical paths through ieu ////\n\n\n" }
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redirect -append $filename { echo "\n\n\n//// Critical paths through ieu ////\n\n\n" }
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@ -445,4 +453,4 @@ set t2 [clock seconds]
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set t [expr $t2 - $t1]
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set t [expr $t2 - $t1]
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echo [expr $t/60]
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echo [expr $t/60]
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quit
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quit
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