From 7b79d8edeb59d676fcef4b54d841d00ff2930f02 Mon Sep 17 00:00:00 2001
From: "James E. Stine" <james.stine@okstate.edu>
Date: Fri, 10 Nov 2023 21:10:35 -0600
Subject: [PATCH] Update scripts/synth.tcl to add with parameter for width and
 also checks wrapper to see if running CONFIG=rv32e to run without WIDTH

---
 synthDC/Makefile          |  6 +++---
 synthDC/scripts/synth.tcl | 14 +++++++++++---
 2 files changed, 14 insertions(+), 6 deletions(-)

diff --git a/synthDC/Makefile b/synthDC/Makefile
index e7918e3dc..8e1b09d01 100755
--- a/synthDC/Makefile
+++ b/synthDC/Makefile
@@ -20,11 +20,11 @@ export MAXCORES ?= 1
 export MAXOPT ?= 0
 export DRIVE ?= FLOP
 export USESRAM ?= 0
-
+export WIDTH ?= 32
 
 time := $(shell date +%F-%H-%M)
 hash := $(shell git rev-parse --short HEAD)
-export OUTPUTDIR := runs/$(DESIGN)_$(CONFIG)_$(MOD)_$(TECH)nm_$(FREQ)_MHz_$(time)_$(TITLE)_$(hash)
+export OUTPUTDIR := runs/$(DESIGN)_$(WIDTH)_$(CONFIG)_$(MOD)_$(TECH)_$(FREQ)_MHz_$(time)_$(TITLE)_$(hash)
 export SAIFPOWER ?= 0
 
 OLDCONFIGDIR ?= ${WALLY}/config
@@ -147,4 +147,4 @@ clean:
 	rm -f power.saif
 	rm -f Synopsys_stack_trace_*.txt
 	rm -f crte_*.txt
-	
\ No newline at end of file
+	
diff --git a/synthDC/scripts/synth.tcl b/synthDC/scripts/synth.tcl
index 9be076edf..cd4d6ff27 100755
--- a/synthDC/scripts/synth.tcl
+++ b/synthDC/scripts/synth.tcl
@@ -18,7 +18,6 @@ suppress_message {VER-274}
 # Enable Multicore
 set_host_options -max_cores $::env(MAXCORES)
 
-
 # get outputDir and configDir from environment (Makefile)
 set outputDir $::env(OUTPUTDIR)
 set cfg $::env(CONFIGDIR)
@@ -26,6 +25,7 @@ set hdl_src "../src"
 set saifpower $::env(SAIFPOWER)
 set maxopt $::env(MAXOPT)
 set drive $::env(DRIVE)
+set width $::env(WIDTH)
 
 eval file copy -force [glob ${cfg}/*.vh] {$outputDir/hdl/}
 eval file copy -force [glob ${hdl_src}/cvw.sv] {$outputDir/hdl/}
@@ -88,7 +88,13 @@ if { [shell_is_in_topographical_mode] } {
 #set alib_library_analysis_path ./$outputDir
 define_design_lib WORK -path ./$outputDir/WORK
 analyze -f sverilog -lib WORK $my_verilog_files
-elaborate $my_toplevel -lib WORK 
+# If wrapper=0, we want to run against a specific module and pass
+# width to DC
+if { $wrapper == 1 } {
+    elaborate $my_toplevel -lib WORK 
+} else {
+    elaborate $my_toplevel -lib WORK -parameters WIDTH=$width
+}
 
 # Set the current_design 
 current_design $my_toplevel
@@ -308,6 +314,8 @@ set filename [format "%s%s" $outputDir  "/reports/mindelay.rep"]
 redirect $filename { report_timing -capacitance -transition_time -nets -delay_type min -nworst 1 }
 
 set filename [format "%s%s" $outputDir  "/reports/per_module_timing.rep"]
+redirect -append $filename { echo "\n\n\n//// Critical paths through Stall ////\n\n\n" }
+redirect -append $filename { report_timing -capacitance -transition_time -nets -through {Stall*} -nworst 1 }
 redirect -append $filename { echo "\n\n\n//// Critical paths through ifu ////\n\n\n" }
 redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ifu/*} -nworst 1 }
 redirect -append $filename { echo "\n\n\n//// Critical paths through ieu ////\n\n\n" }
@@ -445,4 +453,4 @@ set t2 [clock seconds]
 set t [expr $t2 - $t1]
 echo [expr $t/60]
 
-quit 
\ No newline at end of file
+quit