The clock gater was not implemented correctly. Now it is level sensitive to a low clock.

wally-pipelined/src/generic/clockgater.sv

@@ -38,7 +38,7 @@ module clockgater
   logic 	enable_q;
   
 
-  always @(E or SE) begin
+  always @(~CLK) begin
     enable_q <= E | SE;
   end
   assign ECLK = enable_q & CLK;