diff --git a/wally-pipelined/src/generic/clockgater.sv b/wally-pipelined/src/generic/clockgater.sv
index dc51829da..c06a1cbdc 100644
--- a/wally-pipelined/src/generic/clockgater.sv
+++ b/wally-pipelined/src/generic/clockgater.sv
@@ -38,7 +38,7 @@ module clockgater
   logic 	enable_q;
   
 
-  always @(E or SE) begin
+  always @(~CLK) begin
     enable_q <= E | SE;
   end
   assign ECLK = enable_q & CLK;