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Cleaned up unpacker changes in srt and lint errors

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This commit is contained in:
David Harris 2022-05-17 00:06:14 +00:00
parent 017d13c711
commit 7aba83a35c
5 changed files with 19 additions and 12 deletions
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1
.gitignore vendored
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@ -103,3 +103,4 @@ pipelined/config/rv64ic_noMulDiv
pipelined/config/rv64ic_noPriv pipelined/config/rv64ic_noPriv
pipelined/config/rv64ic_orig pipelined/config/rv64ic_orig
synthDC/Summary.csv synthDC/Summary.csv
pipelined/srt/exptestgen

2
pipelined/srt/lint-srt
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@ -1,2 +1,2 @@
verilator --lint-only --top-module srt srt.sv -I../config/rv64gc -I../config/shared ../src/generic/*.sv ../src/generic/flop/*.sv verilator --lint-only --top-module srt srt.sv -I../config/rv64gc -I../config/shared ../src/generic/*.sv ../src/generic/flop/*.sv
verilator --lint-only --top-module testbench testbench.sv -I../config/rv64gc -I../config/shared ../src/generic/*.sv ../src/generic/flop/*.sv ../src/fpu/unpacking.sv verilator --lint-only --top-module testbench testbench.sv -I../config/rv64gc -I../config/shared ../src/generic/*.sv ../src/generic/flop/*.sv ../src/fpu/unpack.sv

2
pipelined/srt/srt.do
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@ -17,7 +17,7 @@ if [file exists work] {
} }
vlib work vlib work
vlog +incdir+../config/rv64gc +incdir+../config/shared srt.sv testbench.sv ../src/generic/flop/flop*.sv ../src/generic/mux.sv ../src/fpu/unpacking.sv vlog +incdir+../config/rv64gc +incdir+../config/shared srt.sv testbench.sv ../src/generic/flop/flop*.sv ../src/generic/mux.sv ../src/fpu/unpack.sv
vopt +acc work.testbench -o workopt vopt +acc work.testbench -o workopt
vsim workopt vsim workopt

3
pipelined/srt/srt.sv
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@ -92,8 +92,9 @@ module srtpostproc #(parameter N=52) (
output [N-1:0] Quot output [N-1:0] Quot
); );
// replace with on-the-fly conversion
//assign Quot = rp - rm; //assign Quot = rp - rm;
finaladd finaladd(rp, rm, Quot); finaladd finaladd(rp, rm, Quot);
endmodule endmodule
module srtpreproc #(parameter Nf=52) ( module srtpreproc #(parameter Nf=52) (

23
pipelined/srt/testbench.sv
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@ -1,7 +1,7 @@
///////////// /////////////
// counter // // divcounter //
///////////// /////////////
module counter(input logic clk, module divcounter(input logic clk,
input logic req, input logic req,
output logic done); output logic done);
@ -36,6 +36,9 @@ endmodule
////////// //////////
// testbench // // testbench //
////////// //////////
/* verilator lint_off STMTDLY */
/* verilator lint_off INFINITELOOP */
module testbench; module testbench;
logic clk; logic clk;
logic req; logic req;
@ -83,11 +86,11 @@ module testbench;
// Unpacker // Unpacker
// Note: BiasE will probably get taken out eventually // Note: BiasE will probably get taken out eventually
unpack unpack(.X({1'b1,a[62:0]}), .Y({1'b1,b[62:0]}), .Z(64'b0), .FmtE(1'b1), .FOpCtrlE(3'b0), unpack unpack(.X({1'b1,a[62:0]}), .Y({1'b1,b[62:0]}), .Z(64'b0), .FmtE(1'b1),
.XSgnE(XSgnE), .YSgnE(YSgnE), .ZSgnE(ZSgnE), .XExpE(XExpE), .YExpE(YExpE), .ZExpE(ZExpE), .XSgnE(XSgnE), .YSgnE(YSgnE), .ZSgnE(ZSgnE), .XExpE(XExpE), .YExpE(YExpE), .ZExpE(ZExpE),
.XManE(XManE), .YManE(YManE), .ZManE(ZManE), .XNormE(XNormE), .XNaNE(XNaNE), .YNaNE(YNaNE), .ZNaNE(ZNaNE), .XManE(XManE), .YManE(YManE), .ZManE(ZManE), .XNormE(XNormE), .XNaNE(XNaNE), .YNaNE(YNaNE), .ZNaNE(ZNaNE),
.XSNaNE(XSNaNE), .YSNaNE(YSNaNE), .ZSNaNE(ZSNaNE), .XDenormE(XDenormE), .YDenormE(YDenormE), .ZDenormE(ZDenormE), .XSNaNE(XSNaNE), .YSNaNE(YSNaNE), .ZSNaNE(ZSNaNE), .XDenormE(XDenormE), .YDenormE(YDenormE), .ZDenormE(ZDenormE),
.XZeroE(XZeroE), .YZeroE(YZeroE), .ZZeroE(ZZeroE), .BiasE(BiasE), .XZeroE(XZeroE), .YZeroE(YZeroE), .ZZeroE(ZZeroE),
.XInfE(XInfE), .YInfE(YInfE), .ZInfE(ZInfE), .XExpMaxE(XExpMaxE)); .XInfE(XInfE), .YInfE(YInfE), .ZInfE(ZInfE), .XExpMaxE(XExpMaxE));
// Divider // Divider
@ -101,8 +104,8 @@ module testbench;
assign result = {1'b0, e, r}; assign result = {1'b0, e, r};
// Counter // Divcounter
counter counter(clk, req, done); divcounter divcounter(clk, req, done);
initial initial
@ -123,7 +126,7 @@ module testbench;
a = Vec[`mema]; a = Vec[`mema];
b = Vec[`memb]; b = Vec[`memb];
nextr = Vec[`memr]; nextr = Vec[`memr];
req <= #5 1; req = #5 1;
end end
// Apply directed test vectors read from file. // Apply directed test vectors read from file.
@ -132,7 +135,7 @@ module testbench;
begin begin
if (done) if (done)
begin begin
req <= #5 1; req = #5 1;
diffp = correctr - result; diffp = correctr - result;
diffn = result - correctr; diffn = result - correctr;
if (($signed(diffn) > 1) | ($signed(diffp) > 1)) // check if accurate to 1 ulp if (($signed(diffn) > 1) | ($signed(diffp) > 1)) // check if accurate to 1 ulp
@ -152,7 +155,7 @@ module testbench;
end end
if (req) if (req)
begin begin
req <= #5 0; req = #5 0;
correctr = nextr; correctr = nextr;
$display("pre increment"); $display("pre increment");
testnum = testnum+1; testnum = testnum+1;
@ -167,3 +170,5 @@ module testbench;
endmodule endmodule
/* verilator lint_on STMTDLY */
/* verilator lint_on INFINITELOOP */