From 7aba83a35c91161578cb93e257ca34ce7ee13207 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Tue, 17 May 2022 00:06:14 +0000
Subject: [PATCH] Cleaned up unpacker changes in srt and lint errors

---
 .gitignore                 |  1 +
 pipelined/srt/lint-srt     |  2 +-
 pipelined/srt/srt.do       |  2 +-
 pipelined/srt/srt.sv       |  3 ++-
 pipelined/srt/testbench.sv | 23 ++++++++++++++---------
 5 files changed, 19 insertions(+), 12 deletions(-)

diff --git a/.gitignore b/.gitignore
index 0a25e7d3d..1e986c3bd 100644
--- a/.gitignore
+++ b/.gitignore
@@ -103,3 +103,4 @@ pipelined/config/rv64ic_noMulDiv
 pipelined/config/rv64ic_noPriv
 pipelined/config/rv64ic_orig
 synthDC/Summary.csv
+pipelined/srt/exptestgen
diff --git a/pipelined/srt/lint-srt b/pipelined/srt/lint-srt
index 8fba602e8..3599cdff5 100755
--- a/pipelined/srt/lint-srt
+++ b/pipelined/srt/lint-srt
@@ -1,2 +1,2 @@
 verilator --lint-only --top-module srt srt.sv -I../config/rv64gc -I../config/shared ../src/generic/*.sv ../src/generic/flop/*.sv
-verilator --lint-only --top-module testbench testbench.sv -I../config/rv64gc -I../config/shared ../src/generic/*.sv ../src/generic/flop/*.sv ../src/fpu/unpacking.sv
+verilator --lint-only --top-module testbench testbench.sv -I../config/rv64gc -I../config/shared ../src/generic/*.sv ../src/generic/flop/*.sv ../src/fpu/unpack.sv
diff --git a/pipelined/srt/srt.do b/pipelined/srt/srt.do
index df969ad49..b4d9bb138 100644
--- a/pipelined/srt/srt.do
+++ b/pipelined/srt/srt.do
@@ -17,7 +17,7 @@ if [file exists work] {
 }
 vlib work
 
-vlog +incdir+../config/rv64gc +incdir+../config/shared srt.sv testbench.sv ../src/generic/flop/flop*.sv ../src/generic/mux.sv ../src/fpu/unpacking.sv
+vlog +incdir+../config/rv64gc +incdir+../config/shared srt.sv testbench.sv ../src/generic/flop/flop*.sv ../src/generic/mux.sv ../src/fpu/unpack.sv
 vopt +acc work.testbench -o workopt 
 vsim workopt
 
diff --git a/pipelined/srt/srt.sv b/pipelined/srt/srt.sv
index bc272b011..81d9e2f25 100644
--- a/pipelined/srt/srt.sv
+++ b/pipelined/srt/srt.sv
@@ -92,8 +92,9 @@ module srtpostproc #(parameter N=52) (
   output [N-1:0] Quot
 );
 
+  // replace with on-the-fly conversion
   //assign Quot = rp - rm;
-  finaladd finaladd(rp, rm, Quot);
+  finaladd finaladd(rp, rm, Quot); 
 endmodule
 
 module srtpreproc #(parameter Nf=52) (
diff --git a/pipelined/srt/testbench.sv b/pipelined/srt/testbench.sv
index 8b3fec51d..9985a89cf 100644
--- a/pipelined/srt/testbench.sv
+++ b/pipelined/srt/testbench.sv
@@ -1,7 +1,7 @@
 /////////////
-// counter //
+// divcounter //
 /////////////
-module counter(input  logic clk, 
+module divcounter(input  logic clk, 
                input  logic req, 
                output logic done);
  
@@ -36,6 +36,9 @@ endmodule
 //////////
 // testbench //
 //////////
+
+/* verilator lint_off STMTDLY */
+/* verilator lint_off INFINITELOOP */
 module testbench;
   logic         clk;
   logic        req;
@@ -83,11 +86,11 @@ module testbench;
 
   // Unpacker
   // Note: BiasE will probably get taken out eventually
-  unpack unpack(.X({1'b1,a[62:0]}), .Y({1'b1,b[62:0]}), .Z(64'b0), .FmtE(1'b1), .FOpCtrlE(3'b0),
+  unpack unpack(.X({1'b1,a[62:0]}), .Y({1'b1,b[62:0]}), .Z(64'b0), .FmtE(1'b1), 
                   .XSgnE(XSgnE), .YSgnE(YSgnE), .ZSgnE(ZSgnE), .XExpE(XExpE), .YExpE(YExpE), .ZExpE(ZExpE),
                   .XManE(XManE), .YManE(YManE), .ZManE(ZManE), .XNormE(XNormE), .XNaNE(XNaNE), .YNaNE(YNaNE), .ZNaNE(ZNaNE),
                   .XSNaNE(XSNaNE), .YSNaNE(YSNaNE), .ZSNaNE(ZSNaNE), .XDenormE(XDenormE), .YDenormE(YDenormE), .ZDenormE(ZDenormE),
-                  .XZeroE(XZeroE), .YZeroE(YZeroE), .ZZeroE(ZZeroE), .BiasE(BiasE),
+                  .XZeroE(XZeroE), .YZeroE(YZeroE), .ZZeroE(ZZeroE), 
                   .XInfE(XInfE), .YInfE(YInfE), .ZInfE(ZInfE), .XExpMaxE(XExpMaxE));
 
   // Divider
@@ -101,8 +104,8 @@ module testbench;
 
   assign result = {1'b0, e, r};
 
-  // Counter
-  counter counter(clk, req, done);
+  // Divcounter
+  divcounter divcounter(clk, req, done);
 
 
     initial
@@ -123,7 +126,7 @@ module testbench;
       a = Vec[`mema];
       b = Vec[`memb];
       nextr = Vec[`memr];
-      req <= #5 1;
+      req = #5 1;
     end
   
   // Apply directed test vectors read from file.
@@ -132,7 +135,7 @@ module testbench;
     begin
       if (done) 
 	begin
-	  req <= #5 1;
+	  req = #5 1;
     diffp = correctr - result;
     diffn = result - correctr;
 	  if (($signed(diffn) > 1) | ($signed(diffp) > 1)) // check if accurate to 1 ulp
@@ -152,7 +155,7 @@ module testbench;
 	end
       if (req) 
 	begin
-	  req <= #5 0;
+	  req = #5 0;
 	  correctr = nextr;
     $display("pre increment");
 	  testnum = testnum+1;
@@ -167,3 +170,5 @@ module testbench;
  
 endmodule
  
+/* verilator lint_on STMTDLY  */
+/* verilator lint_on INFINITELOOP  */