mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Merge branch 'main' of https://github.com/openhwgroup/cvw
This commit is contained in:
Rose Thompson
commit
7a4d485f5b
@ -24,18 +24,18 @@ New users may wish to do the following setup to access the server via a GUI and
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Terminal on Mac, cmd on Windows, xterm on Linux
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See A.1 about ssh -Y login from a terminal
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Then clone the repo, source setup, make the tests and run regression
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Then fork and clone the repo, source setup, make the tests and run regression
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If you don't already have a Github account, create one
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In a web browser, visit https://github.com/openhwgroup/cvw
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In the upper right part of the screen, click on Fork
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Create a fork, choosing the owner as your github account and the repository as cvw.
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Create a fork, choosing the owner as your github account
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and the repository as cvw.
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On the Linux computer where you will be working, log in
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Clone your fork of the repo and run the setup script. Change <yourgithubid> to your github id.
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$ cd
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$ git clone --recurse-submodules https://github.com/<yourgithubid>/cvw
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$ cd cvw
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$ git remote add upstream https://github.com/openhwgroup/cvw
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@ -136,7 +136,13 @@ coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker/adrdecs/iromdec
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coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker/adrdecs/ddr4dec
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coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker/adrdecs/sdcdec
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# PMA Regions 8, 9, and 10 (dtim, irom, ddr4) are never used in the rv64gc configuration, so exclude coverage
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# PMA Regions 1, 2, and 3 (dtim, irom, ddr4) are never used in the rv64gc configuration, so exclude coverage
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set line [GetLineNum ../src/mmu/pmachecker.sv "exclusion-tag: unused-atomic"]
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coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2,4
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coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2,4
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set line [GetLineNum ../src/mmu/pmachecker.sv "exclusion-tag: unused-tim"]
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coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2,4
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coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2,4
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set line [GetLineNum ../src/mmu/pmachecker.sv "exclusion-tag: unused-cachable"]
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coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2
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coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2
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@ -145,11 +151,17 @@ coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker -linerange $line-$lin
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coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2,4,6,8
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# Excluding so far un-used instruction sources for the ifu
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# coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker/adrdecs/bootromdec
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# coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker/adrdecs/uncoreramdec
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coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker/adrdecs/bootromdec
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coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker/adrdecs/uncoreramdec
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coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker/adrdecs/spidec
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#Excluding the bootrom, uncoreran, and clint as sources for the lsu
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# coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/bootromdec
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# The following peripherals are always supported
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set line [GetLineNum ../src/mmu/adrdec.sv "exclusion-tag: adrdecSel"]
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coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/bootromdec -linerange $line-$line -item e 1 -fecexprrow 3,7
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coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/gpiodec -linerange $line-$line -item e 1 -fecexprrow 3
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coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/uartdec -linerange $line-$line -item e 1 -fecexprrow 3
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coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/plicdec -linerange $line-$line -item e 1 -fecexprrow 3
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coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/spidec -linerange $line-$line -item e 1 -fecexprrow 3
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#Excluding signals in lsu: clintdec and uncoreram accept all sizes so 'SizeValid' will never be 0
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set line [GetLineNum ../src/mmu/adrdec.sv "& SizeValid"]
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@ -140,15 +140,12 @@ module unpackinput import cvw::*; #(parameter cvw_t P) (
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endcase
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always_comb
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if (BadNaNBox) begin
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case (Fmt)
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P.FMT: PostBox = In;
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P.FMT1: PostBox = {{(P.FLEN-P.LEN1){1'b1}}, 1'b1, {(P.NE1+1){1'b1}}, {(P.LEN1-P.NE1-2){1'b0}}};
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P.FMT2: PostBox = {{(P.FLEN-P.LEN2){1'b1}}, 1'b1, {(P.NE2+1){1'b1}}, {(P.LEN2-P.NE2-2){1'b0}}};
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default: PostBox = 'x;
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endcase
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end else
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PostBox = In;
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if (BadNaNBox & Fmt == P.FMT1)
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PostBox = {{(P.FLEN-P.LEN1){1'b1}}, 1'b1, {(P.NE1+1){1'b1}}, {(P.LEN1-P.NE1-2){1'b0}}};
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else if (BadNaNBox & Fmt == P.FMT2)
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PostBox = {{(P.FLEN-P.LEN2){1'b1}}, 1'b1, {(P.NE2+1){1'b1}}, {(P.LEN2-P.NE2-2){1'b0}}};
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else
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PostBox = In;
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// extract the sign bit
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always_comb
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@ -49,5 +49,5 @@ module adrdec #(parameter PA_BITS) (
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assign SizeValid = SizeMask[Size];
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// Select this peripheral if the address matches, the peripheral is supported, and the type and size of access is ok
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assign Sel = Match & Supported & AccessValid & SizeValid;
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assign Sel = Match & Supported & AccessValid & SizeValid; // exclusion-tag: adrdecSel
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endmodule
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@ -4,7 +4,8 @@
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// Written: mmendozamanriquez@hmc.edu 4 April 2023
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// nlimpert@hmc.edu
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//
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// Purpose: Test coverage for LSU
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// Purpose: Test coverage for IFU TLB camlines with mismatched ASID values. This file tests odd
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// numbered camlines. tlbASID2.S covers even numbered tlb camlines. These two files are identical.
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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// https://github.com/openhwgroup/cvw
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@ -25,6 +26,8 @@
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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// load code to initalize stack, handle interrupts, terminate
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#include "WALLY-init-lib.h"
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@ -43,11 +46,12 @@ main:
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li t0, 0xC0000000
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li t2, 0 # i = 0
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li t2, 0 # i = 0
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li t5, 0 # j = 0 // now use as a counter for new asid loop
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li t3, 32 # Max amount of Loops = 32
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li t3, 32 # Max amount of Loops = 32
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loop: bge t2, t3, finished # exit loop if i >= loops
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sfence.vma
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li t1, 0x00008067 #load in jalr
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sw t1, 0(t0)
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fence.I
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@ -55,7 +59,7 @@ loop: bge t2, t3, finished # exit loop if i >= loops
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li t5, 0x9001000000080080 // try making asid = 1
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csrw satp, t5
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jalr t0
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li t5, 0x9000000000080080 // try making asid = 0
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li t5, 0x9000000000080080 // try making asid = 0
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csrw satp, t5
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li t4, 0x1000
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add t0, t0, t4
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@ -71,7 +75,7 @@ finished:
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pagetable:
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.8byte 0x200204C1
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.align 12 // level 2 page table, contains direction to a gigapageg
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.align 12 // level 2 page table, contains direction to a gigapage
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.8byte 0x0
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.8byte 0x0
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.8byte 0x200000CF // gigapage that starts at 8000 0000 goes to C000 0000
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@ -55,14 +55,24 @@ main:
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li t4, 0x1000 # address step size
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li a2, 0x80216000 # Test NAPOT pages
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jal a1, looptest
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sfence.vma
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li t4, 0x200000 # address step size
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li a2, 0x80215240 # Test NAPOT pages
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jal a1, looptest
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li a2, 0xC0215240 # Test ill-formed NAPOT pages
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jal a1, looptest
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li a2, 0x40215240 # Test properly formed pages with 1 in PPN[3] that are not NAPOT
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jal a1, looptest
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li a0, 3 # switch back to machine mode because code at 0x80000000 may not have clean page table entry
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ecall
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j done
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looptest:
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mv t0, a2 # base address
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li t2, 0 # i = 0
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li t3, 35 # Max amount of Loops = 34
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li t2, 0 # i = 0
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li t3, 32 # Max amount of Loops = 32
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li t5, 0x8082 # return instruction opcode
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loop: bge t2, t3, finished # exit loop if i >= loops
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