diff --git a/README.md b/README.md
index b9d378fc3..f0b1a9f4b 100644
--- a/README.md
+++ b/README.md
@@ -24,18 +24,18 @@ New users may wish to do the following setup to access the server via a GUI and
 		Terminal on Mac, cmd on Windows, xterm on Linux
 		See A.1 about ssh -Y login from a terminal
 
-Then clone the repo, source setup,  make the tests and run regression
+Then fork and clone the repo, source setup, make the tests and run regression
 
 	If you don't already have a Github account, create one
 	In a web browser, visit https://github.com/openhwgroup/cvw
 	In the upper right part of the screen, click on Fork
-	Create a fork, choosing the owner as your github account and the repository as cvw.
+	Create a fork, choosing the owner as your github account 
+	and the repository as cvw.
 	
 	On the Linux computer where you will be working, log in
 
 Clone your fork of the repo and run the setup script. Change <yourgithubid> to your github id. 
 
-	$ cd
 	$ git clone --recurse-submodules https://github.com/<yourgithubid>/cvw
 	$ cd cvw
 	$ git remote add upstream https://github.com/openhwgroup/cvw
diff --git a/sim/coverage-exclusions-rv64gc.do b/sim/coverage-exclusions-rv64gc.do
index e3ebf636b..907573de4 100644
--- a/sim/coverage-exclusions-rv64gc.do
+++ b/sim/coverage-exclusions-rv64gc.do
@@ -136,7 +136,13 @@ coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker/adrdecs/iromdec
 coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker/adrdecs/ddr4dec
 coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker/adrdecs/sdcdec
 
-# PMA Regions 8, 9, and 10 (dtim, irom, ddr4) are never used in the rv64gc configuration, so exclude coverage
+# PMA Regions 1, 2, and 3 (dtim, irom, ddr4) are never used in the rv64gc configuration, so exclude coverage
+set line [GetLineNum ../src/mmu/pmachecker.sv "exclusion-tag: unused-atomic"]
+coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2,4
+coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2,4
+set line [GetLineNum ../src/mmu/pmachecker.sv "exclusion-tag: unused-tim"]
+coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2,4
+coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2,4
 set line [GetLineNum ../src/mmu/pmachecker.sv "exclusion-tag: unused-cachable"]
 coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2
 coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2
@@ -145,11 +151,17 @@ coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker -linerange $line-$lin
 coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2,4,6,8
 
 # Excluding so far un-used instruction sources for the ifu
-# coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker/adrdecs/bootromdec
-# coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker/adrdecs/uncoreramdec
+coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker/adrdecs/bootromdec
+coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker/adrdecs/uncoreramdec
+coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker/adrdecs/spidec
 
-#Excluding the bootrom, uncoreran, and clint as sources for the lsu
-# coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/bootromdec
+# The following peripherals are always supported
+set line [GetLineNum ../src/mmu/adrdec.sv "exclusion-tag: adrdecSel"]
+coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/bootromdec -linerange $line-$line -item e 1 -fecexprrow 3,7
+coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/gpiodec -linerange $line-$line -item e 1 -fecexprrow 3
+coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/uartdec -linerange $line-$line -item e 1 -fecexprrow 3
+coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/plicdec -linerange $line-$line -item e 1 -fecexprrow 3
+coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/spidec -linerange $line-$line -item e 1 -fecexprrow 3
 
 #Excluding signals in lsu: clintdec and uncoreram accept all sizes so 'SizeValid' will never be 0
 set line [GetLineNum ../src/mmu/adrdec.sv "& SizeValid"]
diff --git a/src/fpu/unpackinput.sv b/src/fpu/unpackinput.sv
index ca58c9d9f..1cdf5a089 100644
--- a/src/fpu/unpackinput.sv
+++ b/src/fpu/unpackinput.sv
@@ -140,15 +140,12 @@ module unpackinput import cvw::*;  #(parameter cvw_t P) (
           endcase
 
       always_comb
-        if (BadNaNBox) begin
-          case (Fmt)
-            P.FMT: PostBox = In;
-            P.FMT1: PostBox = {{(P.FLEN-P.LEN1){1'b1}}, 1'b1, {(P.NE1+1){1'b1}}, {(P.LEN1-P.NE1-2){1'b0}}};
-            P.FMT2: PostBox = {{(P.FLEN-P.LEN2){1'b1}}, 1'b1, {(P.NE2+1){1'b1}}, {(P.LEN2-P.NE2-2){1'b0}}};
-            default: PostBox = 'x;
-          endcase
-        end else 
-          PostBox = In;
+        if (BadNaNBox & Fmt == P.FMT1)
+            PostBox = {{(P.FLEN-P.LEN1){1'b1}}, 1'b1, {(P.NE1+1){1'b1}}, {(P.LEN1-P.NE1-2){1'b0}}};
+        else if (BadNaNBox & Fmt == P.FMT2)
+            PostBox = {{(P.FLEN-P.LEN2){1'b1}}, 1'b1, {(P.NE2+1){1'b1}}, {(P.LEN2-P.NE2-2){1'b0}}};
+        else
+            PostBox = In;
 
       // extract the sign bit
       always_comb
diff --git a/src/mmu/adrdec.sv b/src/mmu/adrdec.sv
index 05ac45bd0..bf092dbc6 100644
--- a/src/mmu/adrdec.sv
+++ b/src/mmu/adrdec.sv
@@ -49,5 +49,5 @@ module adrdec #(parameter PA_BITS) (
   assign SizeValid = SizeMask[Size]; 
   
   // Select this peripheral if the address matches, the peripheral is supported, and the type and size of access is ok
-  assign Sel = Match & Supported & AccessValid & SizeValid;
+  assign Sel = Match & Supported & AccessValid & SizeValid; // exclusion-tag: adrdecSel
 endmodule
diff --git a/tests/coverage/tlbASID.S b/tests/coverage/tlbASID.S
index ecf66feed..25cf650ca 100644
--- a/tests/coverage/tlbASID.S
+++ b/tests/coverage/tlbASID.S
@@ -4,7 +4,8 @@
 // Written: mmendozamanriquez@hmc.edu 4 April 2023
 //          nlimpert@hmc.edu
 //
-// Purpose: Test coverage for LSU
+// Purpose: Test coverage for IFU TLB camlines with mismatched ASID values. This file tests odd
+// numbered camlines. tlbASID2.S covers even numbered tlb camlines. These two files are identical.
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw
@@ -25,6 +26,8 @@
 // and limitations under the License.
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
+
+
 // load code to initalize stack, handle interrupts, terminate
 
 #include "WALLY-init-lib.h"
@@ -43,11 +46,12 @@ main:
 
     li t0, 0xC0000000
 
-    li t2, 0             # i = 0
+    li t2, 0            # i = 0
     li t5, 0            # j = 0 // now use as a counter for new asid loop 
-    li t3, 32     # Max amount of Loops = 32
+    li t3, 32           # Max amount of Loops = 32
 
 loop: bge t2, t3, finished   # exit loop if i >= loops
+    sfence.vma
     li t1, 0x00008067 #load in jalr
     sw t1, 0(t0)
     fence.I
@@ -55,7 +59,7 @@ loop: bge t2, t3, finished   # exit loop if i >= loops
     li t5, 0x9001000000080080 // try making asid = 1 
     csrw satp, t5
     jalr t0
-     li t5, 0x9000000000080080 // try making asid = 0
+    li t5, 0x9000000000080080 // try making asid = 0
     csrw satp, t5
     li t4, 0x1000
     add t0, t0, t4
@@ -71,7 +75,7 @@ finished:
 pagetable: 
     .8byte 0x200204C1
     
-.align 12 // level 2 page table, contains direction to a gigapageg
+.align 12 // level 2 page table, contains direction to a gigapage
     .8byte 0x0
     .8byte 0x0
     .8byte 0x200000CF // gigapage that starts at 8000 0000 goes to C000 0000
diff --git a/tests/coverage/tlbNAPOT.S b/tests/coverage/tlbNAPOT.S
index 56d2943f4..508eb057c 100644
--- a/tests/coverage/tlbNAPOT.S
+++ b/tests/coverage/tlbNAPOT.S
@@ -55,14 +55,24 @@ main:
     li t4, 0x1000     # address step size
     li a2, 0x80216000 # Test NAPOT pages
     jal a1, looptest
+
+    sfence.vma
+    li t4, 0x200000   # address step size
+    li a2, 0x80215240 # Test NAPOT pages
+    jal a1, looptest
+    li a2, 0xC0215240  # Test ill-formed NAPOT pages
+    jal a1, looptest
+    li a2, 0x40215240  # Test properly formed pages with 1 in PPN[3] that are not NAPOT
+    jal a1, looptest
+
     li a0, 3 # switch back to machine mode because code at 0x80000000 may not have clean page table entry
     ecall
     j done
 
 looptest:
     mv t0, a2       # base address
-    li t2, 0             # i = 0
-    li t3, 35     # Max amount of Loops = 34
+    li t2, 0        # i = 0
+    li t3, 32     # Max amount of Loops = 32
     li t5, 0x8082 # return instruction opcode
 
 loop: bge t2, t3, finished   # exit loop if i >= loops