From c93e3c451a18f55cff47bd335c37babb6cd94c0f Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Fri, 25 Aug 2023 17:01:38 -0500 Subject: [PATCH 1/3] Fixed the sdc linux bug which preventing loading the driver. The irq lock was not correctly initalized. --- linux/buildroot-packages/package-source/fpga-axi-sdc.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/linux/buildroot-packages/package-source/fpga-axi-sdc.c b/linux/buildroot-packages/package-source/fpga-axi-sdc.c index 15bd95a90..8bac2c9e5 100644 --- a/linux/buildroot-packages/package-source/fpga-axi-sdc.c +++ b/linux/buildroot-packages/package-source/fpga-axi-sdc.c @@ -272,6 +272,8 @@ static void sdc_reset(struct mmc_host * mmc) { struct sdc_host * host = mmc_priv(mmc); uint32_t card_detect = 0; + spin_lock_init(&host->lock); + spin_lock_irq(&host->lock); sdc_set_clock(host, 400000); @@ -462,7 +464,7 @@ static int axi_sdc_probe(struct platform_device * pdev) { return ret; } - spin_lock_init(&host->lock); + //spin_lock_init(&host->lock); platform_set_drvdata(pdev, host); return 0; From 055e00b8ac35d2a687c3465a2b3b9f669fce550f Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Fri, 25 Aug 2023 17:04:50 -0500 Subject: [PATCH 2/3] Pushed vcu118 to 71MHz. --- fpga/constraints/constraints-vcu118.xdc | 4 ++-- fpga/generator/xlnx_ddr4-vcu118.tcl | 2 +- linux/devicetree/wally-vcu118.dts | 16 +++++++--------- 3 files changed, 10 insertions(+), 12 deletions(-) diff --git a/fpga/constraints/constraints-vcu118.xdc b/fpga/constraints/constraints-vcu118.xdc index 4d185f994..5de479951 100644 --- a/fpga/constraints/constraints-vcu118.xdc +++ b/fpga/constraints/constraints-vcu118.xdc @@ -117,10 +117,10 @@ set_property PULLUP true [get_ports {SDCCmd}] set_input_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 2.500 [get_ports {SDCDat[*]}] -set_input_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 21.000 [get_ports {SDCDat[*]}] +set_input_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 10.000 [get_ports {SDCDat[*]}] set_input_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 2.500 [get_ports {SDCCmd}] -set_input_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 14.000 [get_ports {SDCCmd}] +set_input_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 10.000 [get_ports {SDCCmd}] set_output_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 2.000 [get_ports {SDCCmd}] diff --git a/fpga/generator/xlnx_ddr4-vcu118.tcl b/fpga/generator/xlnx_ddr4-vcu118.tcl index 510c68678..8041726ff 100644 --- a/fpga/generator/xlnx_ddr4-vcu118.tcl +++ b/fpga/generator/xlnx_ddr4-vcu118.tcl @@ -38,7 +38,7 @@ set_property -dict [list CONFIG.C0.ControllerType {DDR4_SDRAM} \ CONFIG.C0.DDR4_AxiNarrowBurst {false} \ CONFIG.Reference_Clock {Differential} \ CONFIG.ADDN_UI_CLKOUT1.INSERT_VIP {0} \ - CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {50} \ + CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {71} \ CONFIG.ADDN_UI_CLKOUT2.INSERT_VIP {0} \ CONFIG.ADDN_UI_CLKOUT2_FREQ_HZ {300} \ CONFIG.ADDN_UI_CLKOUT3.INSERT_VIP {0} \ diff --git a/linux/devicetree/wally-vcu118.dts b/linux/devicetree/wally-vcu118.dts index a4794f0d0..e0257c9a6 100644 --- a/linux/devicetree/wally-vcu118.dts +++ b/linux/devicetree/wally-vcu118.dts @@ -9,20 +9,20 @@ chosen { linux,initrd-end = <0x85c43a00>; linux,initrd-start = <0x84200000>; - bootargs = "root=/dev/vda ro"; + bootargs = "root=/dev/vda ro console=ttyS0,115200"; stdout-path = "/soc/uart@10000000"; }; memory@80000000 { device_type = "memory"; - reg = <0x00 0x80000000 0x00 0x08000000>; + reg = <0x00 0x80000000 0x00 0x10000000>; }; cpus { #address-cells = <0x01>; #size-cells = <0x00>; - clock-frequency = <0x2FAF080>; - timebase-frequency = <0x2FAF080>; + clock-frequency = <0x43B5FC0>; + timebase-frequency = <0x43B5FC0>; cpu@0 { phandle = <0x01>; @@ -51,7 +51,7 @@ uart@10000000 { interrupts = <0x0a>; interrupt-parent = <0x03>; - clock-frequency = <0x2FAF080>; + clock-frequency = <0x43B5FC0>; reg = <0x00 0x10000000 0x00 0x100>; compatible = "ns16550a"; }; @@ -74,10 +74,8 @@ fifo-depth = <256>; bus-width = <4>; interrupt-parent = <0x03>; - clock = <0x2FAF080>; - max-frequency = <0x989680>; - cap-sd-highspeed; - cap-mmc-highspeed; + clock = <0x43B5FC0>; + max-frequency = <0xF4240>; no-sdio; }; From ac0b1fbdb7fc82a314cea6542341d5b3276ec73f Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 29 Aug 2023 08:57:02 -0500 Subject: [PATCH 3/3] Fixed testbench_imperas.sv --- testbench/testbench_imperas.sv | 20 +++++++++----------- 1 file changed, 9 insertions(+), 11 deletions(-) diff --git a/testbench/testbench_imperas.sv b/testbench/testbench_imperas.sv index 0ca45420a..41a6db450 100644 --- a/testbench/testbench_imperas.sv +++ b/testbench/testbench_imperas.sv @@ -60,6 +60,7 @@ module testbench; logic [P.AHBW-1:0] HRDATAEXT; logic HREADYEXT, HRESPEXT; + logic HSELEXTSDC; logic [P.PA_BITS-1:0] HADDR; logic [P.AHBW-1:0] HWDATA; logic [P.XLEN/8-1:0] HWSTRB; @@ -81,13 +82,7 @@ module testbench; logic [31:0] GPIOIN, GPIOOUT, GPIOEN; logic UARTSin, UARTSout; - logic SDCCLK; - logic SDCCmdIn; - logic SDCCmdOut; - logic SDCCmdOE; - logic [3:0] SDCDatIn; - tri1 [3:0] SDCDat; - tri1 SDCCmd; + logic SDCIntr; logic HREADY; logic HSELEXT; @@ -239,6 +234,8 @@ module testbench; end if(P.FPGA) begin : sdcard + // *** fix later +/* -----\/----- EXCLUDED -----\/----- sdModel sdcard (.sdClk(SDCCLK), .cmd(SDCCmd), @@ -247,15 +244,16 @@ module testbench; assign SDCCmd = SDCCmdOE ? SDCCmdOut : 1'bz; assign SDCCmdIn = SDCCmd; assign SDCDatIn = SDCDat; + -----/\----- EXCLUDED -----/\----- */ + assign SDCIntr = '0; end else begin - assign SDCCmd = '0; - assign SDCDat = '0; + assign SDCIntr = '0; end - wallypipelinedsoc #(P) dut(.clk, .reset_ext, .reset, .HRDATAEXT,.HREADYEXT, .HRESPEXT,.HSELEXT, + wallypipelinedsoc #(P) dut(.clk, .reset_ext, .reset, .HRDATAEXT, .HREADYEXT, .HRESPEXT, .HSELEXT, .HSELEXTSDC, .HCLK, .HRESETn, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0), .GPIOIN, .GPIOOUT, .GPIOEN, - .UARTSin, .UARTSout, .SDCCmdIn, .SDCCmdOut, .SDCCmdOE, .SDCDatIn, .SDCCLK); + .UARTSin, .UARTSout, .SDCIntr); // Track names of instructions instrTrackerTB it(clk, reset, dut.core.ieu.dp.FlushE,