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Fix misa synthesis bug (for real now)

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Domenico Ottolia 2021-04-22 15:35:20 -04:00
parent 8baa2a350d
commit 787ae978d7
1 changed files with 3 additions and 1 deletions
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wally-pipelined/src/privileged/csrm.sv
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@ -107,8 +107,10 @@ module csrm #(parameter
logic WritePMPCFG0M, WritePMPCFG2M;
logic WritePMPADDRM [0:15];
localparam MISA_26 = (`MISA) & 32'h03ffffff;
// MISA is hardwired. Spec says it could be written to disable features, but this is not supported by Wally
assign MISA_REGW = {(`XLEN == 32 ? 2'b01 : 2'b10), {(`XLEN-28){1'b0}}, {`MISA}[25:0]};
assign MISA_REGW = {(`XLEN == 32 ? 2'b01 : 2'b10), {(`XLEN-28){1'b0}}, MISA_26[25:0]};
// Write machine Mode CSRs
assign WriteMSTATUSM = CSRMWriteM && (CSRAdrM == MSTATUS);