From 787ae978d796a5949c6e4e27b942afd53d153a9b Mon Sep 17 00:00:00 2001 From: Domenico Ottolia Date: Thu, 22 Apr 2021 15:35:20 -0400 Subject: [PATCH] Fix misa synthesis bug (for real now) --- wally-pipelined/src/privileged/csrm.sv | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/wally-pipelined/src/privileged/csrm.sv b/wally-pipelined/src/privileged/csrm.sv index 1b693e03a..01dd0540a 100644 --- a/wally-pipelined/src/privileged/csrm.sv +++ b/wally-pipelined/src/privileged/csrm.sv @@ -107,8 +107,10 @@ module csrm #(parameter logic WritePMPCFG0M, WritePMPCFG2M; logic WritePMPADDRM [0:15]; + localparam MISA_26 = (`MISA) & 32'h03ffffff; + // MISA is hardwired. Spec says it could be written to disable features, but this is not supported by Wally - assign MISA_REGW = {(`XLEN == 32 ? 2'b01 : 2'b10), {(`XLEN-28){1'b0}}, {`MISA}[25:0]}; + assign MISA_REGW = {(`XLEN == 32 ? 2'b01 : 2'b10), {(`XLEN-28){1'b0}}, MISA_26[25:0]}; // Write machine Mode CSRs assign WriteMSTATUSM = CSRMWriteM && (CSRAdrM == MSTATUS);