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Renaming LSU signals from busdp

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This commit is contained in:
David Harris 2022-08-25 11:05:10 -07:00
parent cd02c894df
commit 78618f5fc0
5 changed files with 27 additions and 31 deletions
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10
pipelined/src/ifu/ifu.sv
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@ -184,10 +184,8 @@ module ifu (
logic [`XLEN-1:0] AllInstrRawF; logic [`XLEN-1:0] AllInstrRawF;
assign InstrRawF = AllInstrRawF[31:0]; assign InstrRawF = AllInstrRawF[31:0];
if (`IROM) begin : irom // *** fix up dtim taking PA_BITS rather than XLEN, *** IEUAdr is a bad name. Probably use a ROM rather than DTIM if (`IROM) begin : irom
irom irom(.clk, .reset, .LSURWM(2'b10), .IEUAdrE(PCNextFSpill), irom irom(.clk, .reset, .Adr(PCNextFSpill), .ReadData(FinalInstrRawF));
.TrapM(1'b0),
.ReadDataWordM({{(`XLEN-32){1'b0}}, FinalInstrRawF}));
assign {BusStall, IFUBusRead} = '0; assign {BusStall, IFUBusRead} = '0;
assign {ICacheStallF, ICacheMiss, ICacheAccess} = '0; assign {ICacheStallF, ICacheMiss, ICacheAccess} = '0;
@ -209,9 +207,9 @@ module ifu (
.WordCount(), .WordCount(),
.CacheFetchLine(ICacheFetchLine), .CacheFetchLine(ICacheFetchLine),
.CacheWriteLine(1'b0), .CacheBusAck(ICacheBusAck), .CacheWriteLine(1'b0), .CacheBusAck(ICacheBusAck),
.FetchBuffer, .LSUPAdrM(PCPF), .FetchBuffer, .PAdrM(PCPF),
.SelUncachedAdr, .SelUncachedAdr,
.IgnoreRequest(ITLBMissF), .LSURWM(2'b10), .CPUBusy, .CacheableM(CacheableF), .IgnoreRequest(ITLBMissF), .RWM(2'b10), .CPUBusy, .CacheableM(CacheableF),
.BusStall, .BusCommittedM()); .BusStall, .BusCommittedM());

10
pipelined/src/ifu/irom.sv
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@ -31,10 +31,8 @@
module irom( module irom(
input logic clk, reset, input logic clk, reset,
input logic [1:0] LSURWM, input logic [`XLEN-1:0] Adr,
input logic [`XLEN-1:0] IEUAdrE, output logic [31:0] ReadData
input logic TrapM,
output logic [`LLEN-1:0] ReadDataWordM
); );
@ -42,7 +40,7 @@ module irom(
localparam ADDR_WDITH = $clog2(`UNCORE_RAM_RANGE/8); // *** this is the wrong size localparam ADDR_WDITH = $clog2(`UNCORE_RAM_RANGE/8); // *** this is the wrong size
localparam OFFSET = $clog2(`LLEN/8); localparam OFFSET = $clog2(`LLEN/8);
brom1p1rw #(`LLEN/8, 8, ADDR_WDITH) brom1p1rw #(ADDR_WDITH, 32)
rom(.clk, .addr(IEUAdrE[ADDR_WDITH+OFFSET-1:OFFSET]), .dout(ReadDataWordM)); rom(.clk, .addr(Adr[ADDR_WDITH+OFFSET-1:OFFSET]), .dout(ReadData));
endmodule endmodule

18
pipelined/src/lsu/busdp.sv
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@ -60,9 +60,9 @@ module busdp #(parameter WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED)
output logic SelUncachedAdr, output logic SelUncachedAdr,
// lsu/ifu interface // lsu/ifu interface
input logic [`PA_BITS-1:0] LSUPAdrM, input logic [`PA_BITS-1:0] PAdrM,
input logic IgnoreRequest, input logic IgnoreRequest,
input logic [1:0] LSURWM, input logic [1:0] RWM,
input logic CPUBusy, input logic CPUBusy,
input logic CacheableM, input logic CacheableM,
input logic [2:0] LSUFunct3M, input logic [2:0] LSUFunct3M,
@ -75,21 +75,21 @@ module busdp #(parameter WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED)
logic [LOGWPL-1:0] WordCountDelayed; logic [LOGWPL-1:0] WordCountDelayed;
logic BufferCaptureEn; logic BufferCaptureEn;
genvar index; genvar index;
for (index = 0; index < WORDSPERLINE; index++) begin:fetchbuffer for (index = 0; index < WORDSPERLINE; index++) begin:fetchbuffer
logic [WORDSPERLINE-1:0] CaptureWord; logic [WORDSPERLINE-1:0] CaptureWord;
assign CaptureWord[index] = BufferCaptureEn & (index == WordCountDelayed); assign CaptureWord[index] = BufferCaptureEn & (index == WordCountDelayed);
flopen #(`XLEN) fb(.clk, .en(CaptureWord[index]), .d(HRDATA), flopen #(`XLEN) fb(.clk, .en(CaptureWord[index]), .d(HRDATA),
.q(FetchBuffer[(index+1)*`XLEN-1:index*`XLEN])); .q(FetchBuffer[(index+1)*`XLEN-1:index*`XLEN]));
end end
mux2 #(`PA_BITS) localadrmux(CacheBusAdr, LSUPAdrM, SelUncachedAdr, LocalHADDR);
mux2 #(`PA_BITS) localadrmux(CacheBusAdr, PAdrM, SelUncachedAdr, LocalHADDR);
assign HADDR = ({{`PA_BITS-LOGWPL{1'b0}}, WordCount} << $clog2(`XLEN/8)) + LocalHADDR; assign HADDR = ({{`PA_BITS-LOGWPL{1'b0}}, WordCount} << $clog2(`XLEN/8)) + LocalHADDR;
mux2 #(3) sizemux(.d0(`XLEN == 32 ? 3'b010 : 3'b011), .d1(LSUFunct3M),
.s(SelUncachedAdr), .y(HSIZE)); mux2 #(3) sizemux(.d0(`XLEN == 32 ? 3'b010 : 3'b011), .d1(LSUFunct3M), .s(SelUncachedAdr), .y(HSIZE));
busfsm #(WordCountThreshold, LOGWPL, CACHE_ENABLED) busfsm( busfsm #(WordCountThreshold, LOGWPL, CACHE_ENABLED) busfsm(
.clk, .reset, .IgnoreRequest, .LSURWM, .CacheFetchLine, .CacheWriteLine, .clk, .reset, .IgnoreRequest, .RWM, .CacheFetchLine, .CacheWriteLine,
.BusAck, .BusInit, .CPUBusy, .CacheableM, .BusStall, .BusWrite, .SelLSUBusWord, .BusRead, .BusAck, .BusInit, .CPUBusy, .CacheableM, .BusStall, .BusWrite, .SelLSUBusWord, .BusRead, .BufferCaptureEn,
.BufferCaptureEn,
.HBURST, .HTRANS, .BusTransComplete, .CacheBusAck, .BusCommittedM, .SelUncachedAdr, .WordCount, .WordCountDelayed); .HBURST, .HTRANS, .BusTransComplete, .CacheBusAck, .BusCommittedM, .SelUncachedAdr, .WordCount, .WordCountDelayed);
endmodule endmodule

16
pipelined/src/lsu/busfsm.sv
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@ -37,7 +37,7 @@ module busfsm #(parameter integer WordCountThreshold,
input logic reset, input logic reset,
input logic IgnoreRequest, input logic IgnoreRequest,
input logic [1:0] LSURWM, input logic [1:0] RWM,
input logic CacheFetchLine, input logic CacheFetchLine,
input logic CacheWriteLine, input logic CacheWriteLine,
input logic BusAck, input logic BusAck,
@ -114,8 +114,8 @@ module busfsm #(parameter integer WordCountThreshold,
always_comb begin always_comb begin
case(BusCurrState) case(BusCurrState)
STATE_BUS_READY: if(IgnoreRequest) BusNextState = STATE_BUS_READY; STATE_BUS_READY: if(IgnoreRequest) BusNextState = STATE_BUS_READY;
else if(LSURWM[0] & UnCachedAccess) BusNextState = STATE_BUS_UNCACHED_WRITE; else if(RWM[0] & UnCachedAccess) BusNextState = STATE_BUS_UNCACHED_WRITE;
else if(LSURWM[1] & UnCachedAccess) BusNextState = STATE_BUS_UNCACHED_READ; else if(RWM[1] & UnCachedAccess) BusNextState = STATE_BUS_UNCACHED_READ;
else if(CacheFetchLine) BusNextState = STATE_BUS_FETCH; else if(CacheFetchLine) BusNextState = STATE_BUS_FETCH;
else if(CacheWriteLine) BusNextState = STATE_BUS_WRITE; else if(CacheWriteLine) BusNextState = STATE_BUS_WRITE;
else BusNextState = STATE_BUS_READY; else BusNextState = STATE_BUS_READY;
@ -160,19 +160,19 @@ module busfsm #(parameter integer WordCountThreshold,
// Reset if we aren't initiating a transaction or if we are finishing a transaction. // Reset if we aren't initiating a transaction or if we are finishing a transaction.
assign CntReset = BusCurrState == STATE_BUS_READY & ~(CacheFetchLine | CacheWriteLine) | BusTransComplete; assign CntReset = BusCurrState == STATE_BUS_READY & ~(CacheFetchLine | CacheWriteLine) | BusTransComplete;
assign BusStall = (BusCurrState == STATE_BUS_READY & ~IgnoreRequest & ((UnCachedAccess & (|LSURWM)) | CacheFetchLine | CacheWriteLine)) | assign BusStall = (BusCurrState == STATE_BUS_READY & ~IgnoreRequest & ((UnCachedAccess & (|RWM)) | CacheFetchLine | CacheWriteLine)) |
(BusCurrState == STATE_BUS_UNCACHED_WRITE) | (BusCurrState == STATE_BUS_UNCACHED_WRITE) |
(BusCurrState == STATE_BUS_UNCACHED_READ) | (BusCurrState == STATE_BUS_UNCACHED_READ) |
(BusCurrState == STATE_BUS_FETCH) | (BusCurrState == STATE_BUS_FETCH) |
(BusCurrState == STATE_BUS_WRITE); (BusCurrState == STATE_BUS_WRITE);
assign UnCachedBusWrite = (BusCurrState == STATE_BUS_READY & UnCachedAccess & LSURWM[0] & ~IgnoreRequest) | assign UnCachedBusWrite = (BusCurrState == STATE_BUS_READY & UnCachedAccess & RWM[0] & ~IgnoreRequest) |
(BusCurrState == STATE_BUS_UNCACHED_WRITE); (BusCurrState == STATE_BUS_UNCACHED_WRITE);
assign BusWrite = UnCachedBusWrite | (BusCurrState == STATE_BUS_WRITE & ~WordCountFlag); assign BusWrite = UnCachedBusWrite | (BusCurrState == STATE_BUS_WRITE & ~WordCountFlag);
assign SelLSUBusWord = (BusCurrState == STATE_BUS_READY & UnCachedAccess & LSURWM[0]) | assign SelLSUBusWord = (BusCurrState == STATE_BUS_READY & UnCachedAccess & RWM[0]) |
(BusCurrState == STATE_BUS_UNCACHED_WRITE) | (BusCurrState == STATE_BUS_UNCACHED_WRITE) |
(BusCurrState == STATE_BUS_WRITE); (BusCurrState == STATE_BUS_WRITE);
assign UnCachedBusRead = (BusCurrState == STATE_BUS_READY & UnCachedAccess & LSURWM[1] & ~IgnoreRequest) | assign UnCachedBusRead = (BusCurrState == STATE_BUS_READY & UnCachedAccess & RWM[1] & ~IgnoreRequest) |
(BusCurrState == STATE_BUS_UNCACHED_READ); (BusCurrState == STATE_BUS_UNCACHED_READ);
assign BusRead = UnCachedBusRead | (BusCurrState == STATE_BUS_FETCH & ~(WordCountFlag)) | (BusCurrState == STATE_BUS_READY & CacheFetchLine); assign BusRead = UnCachedBusRead | (BusCurrState == STATE_BUS_FETCH & ~(WordCountFlag)) | (BusCurrState == STATE_BUS_READY & CacheFetchLine);
assign BufferCaptureEn = UnCachedBusRead | BusCurrState == STATE_BUS_FETCH; assign BufferCaptureEn = UnCachedBusRead | BusCurrState == STATE_BUS_FETCH;
@ -183,7 +183,7 @@ module busfsm #(parameter integer WordCountThreshold,
assign CacheBusAck = (BusCurrState == STATE_BUS_FETCH & WordCountFlag & BusAck) | assign CacheBusAck = (BusCurrState == STATE_BUS_FETCH & WordCountFlag & BusAck) |
(BusCurrState == STATE_BUS_WRITE & WordCountFlag & BusAck); (BusCurrState == STATE_BUS_WRITE & WordCountFlag & BusAck);
assign BusCommittedM = BusCurrState != STATE_BUS_READY; assign BusCommittedM = BusCurrState != STATE_BUS_READY;
assign SelUncachedAdr = (BusCurrState == STATE_BUS_READY & (|LSURWM & UnCachedAccess)) | assign SelUncachedAdr = (BusCurrState == STATE_BUS_READY & (|RWM & UnCachedAccess)) |
(BusCurrState == STATE_BUS_UNCACHED_READ | (BusCurrState == STATE_BUS_UNCACHED_READ |
BusCurrState == STATE_BUS_UNCACHED_READ_DONE | BusCurrState == STATE_BUS_UNCACHED_READ_DONE |
BusCurrState == STATE_BUS_UNCACHED_WRITE | BusCurrState == STATE_BUS_UNCACHED_WRITE |

4
pipelined/src/lsu/lsu.sv
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@ -228,8 +228,8 @@ module lsu (
.BusRead(LSUBusRead), .HSIZE(LSUHSIZE), .HBURST(LSUHBURST), .HTRANS(LSUHTRANS), .BusTransComplete(LSUTransComplete), .BusRead(LSUBusRead), .HSIZE(LSUHSIZE), .HBURST(LSUHBURST), .HTRANS(LSUHTRANS), .BusTransComplete(LSUTransComplete),
.WordCount, .SelLSUBusWord, .WordCount, .SelLSUBusWord,
.LSUFunct3M, .HADDR(LSUHADDR), .CacheBusAdr(DCacheBusAdr), .CacheFetchLine(DCacheFetchLine), .LSUFunct3M, .HADDR(LSUHADDR), .CacheBusAdr(DCacheBusAdr), .CacheFetchLine(DCacheFetchLine),
.CacheWriteLine(DCacheWriteLine), .CacheBusAck(DCacheBusAck), .FetchBuffer, .LSUPAdrM, .CacheWriteLine(DCacheWriteLine), .CacheBusAck(DCacheBusAck), .FetchBuffer, .PAdrM(LSUPAdrM),
.SelUncachedAdr, .IgnoreRequest, .LSURWM, .CPUBusy, .CacheableM, .SelUncachedAdr, .IgnoreRequest, .RWM(LSURWM), .CPUBusy, .CacheableM,
.BusStall, .BusCommittedM); .BusStall, .BusCommittedM);
mux2 #(`LLEN) UnCachedDataMux(.d0(LittleEndianReadDataWordM), .d1({{`LLEN-`XLEN{1'b0}}, FetchBuffer[`XLEN-1:0]}), mux2 #(`LLEN) UnCachedDataMux(.d0(LittleEndianReadDataWordM), .d1({{`LLEN-`XLEN{1'b0}}, FetchBuffer[`XLEN-1:0]}),