diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv
index 442d23d29..aab3ad00d 100644
--- a/pipelined/src/ifu/ifu.sv
+++ b/pipelined/src/ifu/ifu.sv
@@ -184,10 +184,8 @@ module ifu (
logic [`XLEN-1:0] AllInstrRawF;
assign InstrRawF = AllInstrRawF[31:0];
- if (`IROM) begin : irom // *** fix up dtim taking PA_BITS rather than XLEN, *** IEUAdr is a bad name. Probably use a ROM rather than DTIM
- irom irom(.clk, .reset, .LSURWM(2'b10), .IEUAdrE(PCNextFSpill),
- .TrapM(1'b0),
- .ReadDataWordM({{(`XLEN-32){1'b0}}, FinalInstrRawF}));
+ if (`IROM) begin : irom
+ irom irom(.clk, .reset, .Adr(PCNextFSpill), .ReadData(FinalInstrRawF));
assign {BusStall, IFUBusRead} = '0;
assign {ICacheStallF, ICacheMiss, ICacheAccess} = '0;
@@ -209,9 +207,9 @@ module ifu (
.WordCount(),
.CacheFetchLine(ICacheFetchLine),
.CacheWriteLine(1'b0), .CacheBusAck(ICacheBusAck),
- .FetchBuffer, .LSUPAdrM(PCPF),
+ .FetchBuffer, .PAdrM(PCPF),
.SelUncachedAdr,
- .IgnoreRequest(ITLBMissF), .LSURWM(2'b10), .CPUBusy, .CacheableM(CacheableF),
+ .IgnoreRequest(ITLBMissF), .RWM(2'b10), .CPUBusy, .CacheableM(CacheableF),
.BusStall, .BusCommittedM());
diff --git a/pipelined/src/ifu/irom.sv b/pipelined/src/ifu/irom.sv
index fccc916d9..83585c07e 100644
--- a/pipelined/src/ifu/irom.sv
+++ b/pipelined/src/ifu/irom.sv
@@ -31,10 +31,8 @@
module irom(
input logic clk, reset,
- input logic [1:0] LSURWM,
- input logic [`XLEN-1:0] IEUAdrE,
- input logic TrapM,
- output logic [`LLEN-1:0] ReadDataWordM
+ input logic [`XLEN-1:0] Adr,
+ output logic [31:0] ReadData
);
@@ -42,7 +40,7 @@ module irom(
localparam ADDR_WDITH = $clog2(`UNCORE_RAM_RANGE/8); // *** this is the wrong size
localparam OFFSET = $clog2(`LLEN/8);
- brom1p1rw #(`LLEN/8, 8, ADDR_WDITH)
- rom(.clk, .addr(IEUAdrE[ADDR_WDITH+OFFSET-1:OFFSET]), .dout(ReadDataWordM));
+ brom1p1rw #(ADDR_WDITH, 32)
+ rom(.clk, .addr(Adr[ADDR_WDITH+OFFSET-1:OFFSET]), .dout(ReadData));
endmodule
diff --git a/pipelined/src/lsu/busdp.sv b/pipelined/src/lsu/busdp.sv
index cb216e718..8da148abb 100644
--- a/pipelined/src/lsu/busdp.sv
+++ b/pipelined/src/lsu/busdp.sv
@@ -60,9 +60,9 @@ module busdp #(parameter WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED)
output logic SelUncachedAdr,
// lsu/ifu interface
- input logic [`PA_BITS-1:0] LSUPAdrM,
+ input logic [`PA_BITS-1:0] PAdrM,
input logic IgnoreRequest,
- input logic [1:0] LSURWM,
+ input logic [1:0] RWM,
input logic CPUBusy,
input logic CacheableM,
input logic [2:0] LSUFunct3M,
@@ -75,21 +75,21 @@ module busdp #(parameter WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED)
logic [LOGWPL-1:0] WordCountDelayed;
logic BufferCaptureEn;
- genvar index;
+ genvar index;
for (index = 0; index < WORDSPERLINE; index++) begin:fetchbuffer
logic [WORDSPERLINE-1:0] CaptureWord;
assign CaptureWord[index] = BufferCaptureEn & (index == WordCountDelayed);
flopen #(`XLEN) fb(.clk, .en(CaptureWord[index]), .d(HRDATA),
.q(FetchBuffer[(index+1)*`XLEN-1:index*`XLEN]));
end
- mux2 #(`PA_BITS) localadrmux(CacheBusAdr, LSUPAdrM, SelUncachedAdr, LocalHADDR);
+
+ mux2 #(`PA_BITS) localadrmux(CacheBusAdr, PAdrM, SelUncachedAdr, LocalHADDR);
assign HADDR = ({{`PA_BITS-LOGWPL{1'b0}}, WordCount} << $clog2(`XLEN/8)) + LocalHADDR;
- mux2 #(3) sizemux(.d0(`XLEN == 32 ? 3'b010 : 3'b011), .d1(LSUFunct3M),
- .s(SelUncachedAdr), .y(HSIZE));
+
+ mux2 #(3) sizemux(.d0(`XLEN == 32 ? 3'b010 : 3'b011), .d1(LSUFunct3M), .s(SelUncachedAdr), .y(HSIZE));
busfsm #(WordCountThreshold, LOGWPL, CACHE_ENABLED) busfsm(
- .clk, .reset, .IgnoreRequest, .LSURWM, .CacheFetchLine, .CacheWriteLine,
- .BusAck, .BusInit, .CPUBusy, .CacheableM, .BusStall, .BusWrite, .SelLSUBusWord, .BusRead,
- .BufferCaptureEn,
+ .clk, .reset, .IgnoreRequest, .RWM, .CacheFetchLine, .CacheWriteLine,
+ .BusAck, .BusInit, .CPUBusy, .CacheableM, .BusStall, .BusWrite, .SelLSUBusWord, .BusRead, .BufferCaptureEn,
.HBURST, .HTRANS, .BusTransComplete, .CacheBusAck, .BusCommittedM, .SelUncachedAdr, .WordCount, .WordCountDelayed);
endmodule
diff --git a/pipelined/src/lsu/busfsm.sv b/pipelined/src/lsu/busfsm.sv
index e86f76788..f95f77dd0 100644
--- a/pipelined/src/lsu/busfsm.sv
+++ b/pipelined/src/lsu/busfsm.sv
@@ -37,7 +37,7 @@ module busfsm #(parameter integer WordCountThreshold,
input logic reset,
input logic IgnoreRequest,
- input logic [1:0] LSURWM,
+ input logic [1:0] RWM,
input logic CacheFetchLine,
input logic CacheWriteLine,
input logic BusAck,
@@ -114,8 +114,8 @@ module busfsm #(parameter integer WordCountThreshold,
always_comb begin
case(BusCurrState)
STATE_BUS_READY: if(IgnoreRequest) BusNextState = STATE_BUS_READY;
- else if(LSURWM[0] & UnCachedAccess) BusNextState = STATE_BUS_UNCACHED_WRITE;
- else if(LSURWM[1] & UnCachedAccess) BusNextState = STATE_BUS_UNCACHED_READ;
+ else if(RWM[0] & UnCachedAccess) BusNextState = STATE_BUS_UNCACHED_WRITE;
+ else if(RWM[1] & UnCachedAccess) BusNextState = STATE_BUS_UNCACHED_READ;
else if(CacheFetchLine) BusNextState = STATE_BUS_FETCH;
else if(CacheWriteLine) BusNextState = STATE_BUS_WRITE;
else BusNextState = STATE_BUS_READY;
@@ -160,19 +160,19 @@ module busfsm #(parameter integer WordCountThreshold,
// Reset if we aren't initiating a transaction or if we are finishing a transaction.
assign CntReset = BusCurrState == STATE_BUS_READY & ~(CacheFetchLine | CacheWriteLine) | BusTransComplete;
- assign BusStall = (BusCurrState == STATE_BUS_READY & ~IgnoreRequest & ((UnCachedAccess & (|LSURWM)) | CacheFetchLine | CacheWriteLine)) |
+ assign BusStall = (BusCurrState == STATE_BUS_READY & ~IgnoreRequest & ((UnCachedAccess & (|RWM)) | CacheFetchLine | CacheWriteLine)) |
(BusCurrState == STATE_BUS_UNCACHED_WRITE) |
(BusCurrState == STATE_BUS_UNCACHED_READ) |
(BusCurrState == STATE_BUS_FETCH) |
(BusCurrState == STATE_BUS_WRITE);
- assign UnCachedBusWrite = (BusCurrState == STATE_BUS_READY & UnCachedAccess & LSURWM[0] & ~IgnoreRequest) |
+ assign UnCachedBusWrite = (BusCurrState == STATE_BUS_READY & UnCachedAccess & RWM[0] & ~IgnoreRequest) |
(BusCurrState == STATE_BUS_UNCACHED_WRITE);
assign BusWrite = UnCachedBusWrite | (BusCurrState == STATE_BUS_WRITE & ~WordCountFlag);
- assign SelLSUBusWord = (BusCurrState == STATE_BUS_READY & UnCachedAccess & LSURWM[0]) |
+ assign SelLSUBusWord = (BusCurrState == STATE_BUS_READY & UnCachedAccess & RWM[0]) |
(BusCurrState == STATE_BUS_UNCACHED_WRITE) |
(BusCurrState == STATE_BUS_WRITE);
- assign UnCachedBusRead = (BusCurrState == STATE_BUS_READY & UnCachedAccess & LSURWM[1] & ~IgnoreRequest) |
+ assign UnCachedBusRead = (BusCurrState == STATE_BUS_READY & UnCachedAccess & RWM[1] & ~IgnoreRequest) |
(BusCurrState == STATE_BUS_UNCACHED_READ);
assign BusRead = UnCachedBusRead | (BusCurrState == STATE_BUS_FETCH & ~(WordCountFlag)) | (BusCurrState == STATE_BUS_READY & CacheFetchLine);
assign BufferCaptureEn = UnCachedBusRead | BusCurrState == STATE_BUS_FETCH;
@@ -183,7 +183,7 @@ module busfsm #(parameter integer WordCountThreshold,
assign CacheBusAck = (BusCurrState == STATE_BUS_FETCH & WordCountFlag & BusAck) |
(BusCurrState == STATE_BUS_WRITE & WordCountFlag & BusAck);
assign BusCommittedM = BusCurrState != STATE_BUS_READY;
- assign SelUncachedAdr = (BusCurrState == STATE_BUS_READY & (|LSURWM & UnCachedAccess)) |
+ assign SelUncachedAdr = (BusCurrState == STATE_BUS_READY & (|RWM & UnCachedAccess)) |
(BusCurrState == STATE_BUS_UNCACHED_READ |
BusCurrState == STATE_BUS_UNCACHED_READ_DONE |
BusCurrState == STATE_BUS_UNCACHED_WRITE |
diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv
index 5ec268223..92b82d817 100644
--- a/pipelined/src/lsu/lsu.sv
+++ b/pipelined/src/lsu/lsu.sv
@@ -228,8 +228,8 @@ module lsu (
.BusRead(LSUBusRead), .HSIZE(LSUHSIZE), .HBURST(LSUHBURST), .HTRANS(LSUHTRANS), .BusTransComplete(LSUTransComplete),
.WordCount, .SelLSUBusWord,
.LSUFunct3M, .HADDR(LSUHADDR), .CacheBusAdr(DCacheBusAdr), .CacheFetchLine(DCacheFetchLine),
- .CacheWriteLine(DCacheWriteLine), .CacheBusAck(DCacheBusAck), .FetchBuffer, .LSUPAdrM,
- .SelUncachedAdr, .IgnoreRequest, .LSURWM, .CPUBusy, .CacheableM,
+ .CacheWriteLine(DCacheWriteLine), .CacheBusAck(DCacheBusAck), .FetchBuffer, .PAdrM(LSUPAdrM),
+ .SelUncachedAdr, .IgnoreRequest, .RWM(LSURWM), .CPUBusy, .CacheableM,
.BusStall, .BusCommittedM);
mux2 #(`LLEN) UnCachedDataMux(.d0(LittleEndianReadDataWordM), .d1({{`LLEN-`XLEN{1'b0}}, FetchBuffer[`XLEN-1:0]}),