Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-02-11 06:05:49 +00:00
Code Issues Packages Projects Releases Wiki Activity

Merge branch 'main' into lrufixes

Browse Source
This commit is contained in:
Rose Thompson 2024-11-13 10:34:21 -06:00
commit 77d47e531f
1 changed files with 10 additions and 9 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
testbench/common/loggers.sv
View File

@ -46,12 +46,13 @@ module loggers import cvw::*; #(parameter cvw_t P,
// performance counter logging
logic BeginSample;
logic StartSample, EndSample;
if((PrintHPMCounters || BPRED_LOGGER) && P.ZICNTR_SUPPORTED) begin : HPMCSample
if((PrintHPMCounters | BPRED_LOGGER) & P.ZICNTR_SUPPORTED) begin : HPMCSample
integer HPMCindex;
logic StartSampleFirst;
logic StartSampleDelayed, BeginDelayed;
logic EndSampleFirst;
logic [P.XLEN-1:0] InitialHPMCOUNTERH[P.COUNTERS-1:0];
logic EndSampleDelayed;
string HPMCnames[] = '{"Mcycle",
"------",
@ -80,6 +81,7 @@ module loggers import cvw::*; #(parameter cvw_t P,
"Divide Cycles"
};
always_comb
if (TEST == "embench") begin
StartSampleFirst = FunctionName.FunctionName.FunctionName == "start_trigger";
@ -92,13 +94,12 @@ module loggers import cvw::*; #(parameter cvw_t P,
EndSampleFirst = '0;
end
// this code needs to be with embench and coremark but not the else condition
if (TEST == "embench" | TEST == "coremark") begin
logic EndSampleDelayed;
flopr #(1) EndSampleReg(clk, reset, EndSampleFirst, EndSampleDelayed);
assign EndSample = EndSampleFirst & ~ EndSampleDelayed;
always_comb
if (TEST == "embench" | TEST == "coremark") begin
EndSample = EndSampleFirst & ~ EndSampleDelayed;
end else begin
assign EndSample = DCacheFlushStart & ~DCacheFlushDone;
EndSample = DCacheFlushStart & ~DCacheFlushDone;
end
/*