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https://github.com/openhwgroup/cvw
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classify unit created and passes imperas tests
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@ -162,7 +162,6 @@ module fpu (
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// classify signals
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// classify signals
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logic [63:0] ClassResultE, ClassResultM, ClassResultW;
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logic [63:0] ClassResultE, ClassResultM, ClassResultW;
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logic [4:0] ClassFlagsE, ClassFlagsM, ClassFlagsW;
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// other
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// other
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logic [63:0] FPUResult64W, FPUResult64E; // 64-bit FPU result
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logic [63:0] FPUResult64W, FPUResult64E; // 64-bit FPU result
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@ -287,6 +286,11 @@ module fpu (
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//first and only instance of floating-point sign converter
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//first and only instance of floating-point sign converter
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fpusgn fpsgn (.SgnOpCodeE(FOpCtrlE[1:0]),.*);
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fpusgn fpsgn (.SgnOpCodeE(FOpCtrlE[1:0]),.*);
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//first and only instance of floating-point classify unit
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fpuclassify fpuclass (.*);
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@ -394,7 +398,10 @@ module fpu (
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flopenrc #(1) EMReg7(clk, reset, PipeClearEM, PipeEnableEM, FWriteIntE, FWriteIntM);
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flopenrc #(1) EMReg7(clk, reset, PipeClearEM, PipeEnableEM, FWriteIntE, FWriteIntM);
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flopenrc #(2) EMReg8(clk, reset, PipeClearEM, PipeEnableEM, FMemRWE, FMemRWM);
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flopenrc #(2) EMReg8(clk, reset, PipeClearEM, PipeEnableEM, FMemRWE, FMemRWM);
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//*****************
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//fpuclassify E/M pipe registers
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//*****************
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flopenrc #(64) EMRegClass(clk, reset, PipeClearEM, PipeEnableEM, ClassResultE, ClassResultM);
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@ -471,6 +478,10 @@ module fpu (
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flopenrc #(1) MWReg7(clk, reset, PipeClearMW, PipeEnableMW, FWriteIntM, FWriteIntW);
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flopenrc #(1) MWReg7(clk, reset, PipeClearMW, PipeEnableMW, FWriteIntM, FWriteIntW);
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//*****************
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//fpuclassify M/W pipe registers
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//*****************
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flopenrc #(64) MWRegClass(clk, reset, PipeClearMW, PipeEnableMW, ClassResultM, ClassResultW);
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@ -496,7 +507,7 @@ module fpu (
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// add/sub/cnvt
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// add/sub/cnvt
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3'b100 : FPUFlagsW = FAddFlagsW;
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3'b100 : FPUFlagsW = FAddFlagsW;
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// classify
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// classify
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3'b101 : FPUFlagsW = ClassFlagsW;
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3'b101 : FPUFlagsW = 5'b0;
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// output SrcAW
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// output SrcAW
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3'b110 : FPUFlagsW = 5'b0;
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3'b110 : FPUFlagsW = 5'b0;
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// output FRD1
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// output FRD1
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50
wally-pipelined/src/fpu/fpuclassify.sv
Normal file
50
wally-pipelined/src/fpu/fpuclassify.sv
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@ -0,0 +1,50 @@
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`include "wally-config.vh"
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module fpuclassify (
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input logic [63:0] FInput1E,
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input logic FmtE, // 0-single 1-double
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output logic [63:0] ClassResultE
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);
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logic [31:0] single;
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logic [63:0] double;
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logic sign;
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logic infinity, NaN, zero, normal, subnormal;
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logic ExpNotZero, ExpOnes, ManNotZero, ExpZero, ManZero, FirstBitMan;
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// single and double precision layouts
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assign single = FInput1E[63:32];
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assign double = FInput1E;
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assign sign = FInput1E[63];
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// basic calculations for readabillity
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assign ExpNotZero = FmtE ? |double[62:52] : |single[30:23];
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assign ExpZero = ~ExpNotZero;
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assign ExpOnes = FmtE ? &double[62:52] : &single[30:23];
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assign ManNotZero = FmtE ? |double[51:0] : |single[22:0];
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assign ManZero = ~ManNotZero;
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assign FirstBitMan = FmtE ? double[51] : single[22];
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// determine the type of number
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assign NaN = ExpOnes & ManNotZero;
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assign infinity = ExpOnes & ManZero;
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assign zero = ExpZero & ManZero;
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assign subnormal= ExpZero & ManNotZero;
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assign normal = ExpNotZero;
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// determine sub category and combine into the result
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// bit 0 - -infinity
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// bit 1 - -normal
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// bit 2 - -subnormal
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// bit 3 - -zero
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// bit 4 - +zero
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// bit 5 - +subnormal
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// bit 6 - +normal
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// bit 7 - +infinity
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// bit 8 - signaling NaN
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// bit 9 - quiet NaN
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assign ClassResultE = {{`XLEN-10{1'b0}}, FirstBitMan&NaN, ~FirstBitMan&NaN, ~sign&infinity, ~sign&normal,
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~sign&subnormal, ~sign&zero, sign&zero, sign&subnormal, sign&normal, sign&infinity, {64-`XLEN{1'b0}}};
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endmodule
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@ -124,7 +124,7 @@ string tests32f[] = '{
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"rv64d/I-FLT-D-01", "2000",
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"rv64d/I-FLT-D-01", "2000",
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"rv64d/I-FEQ-D-01", "2000",
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"rv64d/I-FEQ-D-01", "2000",
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"rv64d/I-FADD-D-01", "2000",
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"rv64d/I-FADD-D-01", "2000",
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// "rv64d/I-FCLASS-D-01", "2000",
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"rv64d/I-FCLASS-D-01", "2000",
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// "rv64d/I-FCVT-D-L-01", "2000",
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// "rv64d/I-FCVT-D-L-01", "2000",
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// "rv64d/I-FCVT-D-LU-01", "2000",
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// "rv64d/I-FCVT-D-LU-01", "2000",
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// "rv64d/I-FCVT-D-S-01", "2000",
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// "rv64d/I-FCVT-D-S-01", "2000",
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@ -653,7 +653,7 @@ string tests32f[] = '{
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errors = errors+1;
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errors = errors+1;
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$display(" Error on test %s result %d: adr = %h sim = %h, signature = %h",
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$display(" Error on test %s result %d: adr = %h sim = %h, signature = %h",
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tests[test], i, (testadr+i)*`XLEN/8, dut.uncore.dtim.RAM[testadr+i], signature[i]);
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tests[test], i, (testadr+i)*`XLEN/8, dut.uncore.dtim.RAM[testadr+i], signature[i]);
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// $stop;//***debug
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$stop;//***debug
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end
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end
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end
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end
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i = i + 1;
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i = i + 1;
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