From 778ba6bbf5e7ae8c7d680941043bd41a344af76f Mon Sep 17 00:00:00 2001
From: Katherine Parry <kparry4@gmail.com>
Date: Thu, 27 May 2021 18:53:55 -0400
Subject: [PATCH] classify unit created and passes imperas tests

---
 wally-pipelined/src/fpu/fpu.sv                | 17 +++++--
 wally-pipelined/src/fpu/fpuclassify.sv        | 50 +++++++++++++++++++
 .../testbench/testbench-imperas.sv            |  4 +-
 3 files changed, 66 insertions(+), 5 deletions(-)
 create mode 100644 wally-pipelined/src/fpu/fpuclassify.sv

diff --git a/wally-pipelined/src/fpu/fpu.sv b/wally-pipelined/src/fpu/fpu.sv
index aa1039bed..c876b3131 100755
--- a/wally-pipelined/src/fpu/fpu.sv
+++ b/wally-pipelined/src/fpu/fpu.sv
@@ -162,7 +162,6 @@ module fpu (
 
   // classify signals
   logic [63:0]      ClassResultE, ClassResultM, ClassResultW;
-  logic [4:0]       ClassFlagsE, ClassFlagsM, ClassFlagsW;
 
   // other
   logic [63:0]      FPUResult64W, FPUResult64E;                                           // 64-bit FPU result
@@ -287,6 +286,11 @@ module fpu (
   //first and only instance of floating-point sign converter
   fpusgn fpsgn (.SgnOpCodeE(FOpCtrlE[1:0]),.*);
 
+  //first and only instance of floating-point classify unit
+  fpuclassify fpuclass (.*);
+
+  
+
 
 
 
@@ -394,7 +398,10 @@ module fpu (
   flopenrc #(1) EMReg7(clk, reset, PipeClearEM, PipeEnableEM, FWriteIntE, FWriteIntM);
   flopenrc #(2) EMReg8(clk, reset, PipeClearEM, PipeEnableEM, FMemRWE, FMemRWM);
 
-
+  //*****************
+  //fpuclassify E/M pipe registers
+  //***************** 
+  flopenrc #(64) EMRegClass(clk, reset, PipeClearEM, PipeEnableEM, ClassResultE, ClassResultM);
 
 
 
@@ -471,6 +478,10 @@ module fpu (
   flopenrc #(1) MWReg7(clk, reset, PipeClearMW, PipeEnableMW, FWriteIntM, FWriteIntW);
 
 
+  //*****************
+  //fpuclassify M/W pipe registers
+  //***************** 
+  flopenrc #(64) MWRegClass(clk, reset, PipeClearMW, PipeEnableMW, ClassResultM, ClassResultW);
 
 
 
@@ -496,7 +507,7 @@ module fpu (
 		// add/sub/cnvt
 		3'b100 : FPUFlagsW = FAddFlagsW;
 		// classify
-		3'b101 : FPUFlagsW = ClassFlagsW;
+		3'b101 : FPUFlagsW = 5'b0;
 		// output SrcAW
 		3'b110 : FPUFlagsW = 5'b0;
 		// output FRD1
diff --git a/wally-pipelined/src/fpu/fpuclassify.sv b/wally-pipelined/src/fpu/fpuclassify.sv
new file mode 100644
index 000000000..ee03cb52b
--- /dev/null
+++ b/wally-pipelined/src/fpu/fpuclassify.sv
@@ -0,0 +1,50 @@
+`include "wally-config.vh"
+
+module fpuclassify (
+    input  logic [63:0] FInput1E,
+    input  logic        FmtE,           // 0-single 1-double
+    output logic [63:0] ClassResultE
+    );
+
+    logic [31:0] single;
+    logic [63:0] double;
+    logic sign;
+    logic infinity, NaN, zero, normal, subnormal;
+    logic ExpNotZero, ExpOnes, ManNotZero, ExpZero, ManZero, FirstBitMan;
+   
+    // single and double precision layouts
+    assign single = FInput1E[63:32];
+    assign double = FInput1E;
+    assign sign = FInput1E[63];
+
+    // basic calculations for readabillity
+    assign ExpNotZero = FmtE ? |double[62:52] : |single[30:23];
+    assign ExpZero = ~ExpNotZero;
+    assign ExpOnes = FmtE ? &double[62:52] : &single[30:23];
+    assign ManNotZero = FmtE ? |double[51:0] : |single[22:0];
+    assign ManZero = ~ManNotZero;
+    assign FirstBitMan = FmtE ? double[51] : single[22];
+
+    // determine the type of number
+    assign NaN      = ExpOnes & ManNotZero;
+    assign infinity = ExpOnes & ManZero;
+    assign zero     = ExpZero & ManZero;
+    assign subnormal= ExpZero & ManNotZero;
+    assign normal   = ExpNotZero;
+
+    // determine sub category and combine into the result
+    //  bit 0 - -infinity
+    //  bit 1 - -normal
+    //  bit 2 - -subnormal
+    //  bit 3 - -zero
+    //  bit 4 - +zero
+    //  bit 5 - +subnormal
+    //  bit 6 - +normal
+    //  bit 7 - +infinity
+    //  bit 8 - signaling NaN
+    //  bit 9 - quiet NaN
+    assign ClassResultE = {{`XLEN-10{1'b0}}, FirstBitMan&NaN, ~FirstBitMan&NaN, ~sign&infinity, ~sign&normal, 
+                                    ~sign&subnormal, ~sign&zero, sign&zero, sign&subnormal, sign&normal, sign&infinity, {64-`XLEN{1'b0}}};
+
+
+endmodule
diff --git a/wally-pipelined/testbench/testbench-imperas.sv b/wally-pipelined/testbench/testbench-imperas.sv
index b8f97b267..c5abff91d 100644
--- a/wally-pipelined/testbench/testbench-imperas.sv
+++ b/wally-pipelined/testbench/testbench-imperas.sv
@@ -124,7 +124,7 @@ string tests32f[] = '{
     "rv64d/I-FLT-D-01", "2000",
     "rv64d/I-FEQ-D-01", "2000",
     "rv64d/I-FADD-D-01", "2000",
-    // "rv64d/I-FCLASS-D-01", "2000",
+    "rv64d/I-FCLASS-D-01", "2000",
     // "rv64d/I-FCVT-D-L-01", "2000",
     // "rv64d/I-FCVT-D-LU-01", "2000",
     // "rv64d/I-FCVT-D-S-01", "2000",
@@ -653,7 +653,7 @@ string tests32f[] = '{
               errors = errors+1;
               $display("  Error on test %s result %d: adr = %h sim = %h, signature = %h", 
                     tests[test], i, (testadr+i)*`XLEN/8, dut.uncore.dtim.RAM[testadr+i], signature[i]);
-              // $stop;//***debug
+              $stop;//***debug
             end
           end
           i = i + 1;