diff --git a/config/rv32e/config.vh b/config/rv32e/config.vh index 5e1f883d4..163ef316b 100644 --- a/config/rv32e/config.vh +++ b/config/rv32e/config.vh @@ -51,6 +51,8 @@ localparam ZICOND_SUPPORTED = 0; localparam SVPBMT_SUPPORTED = 0; localparam SVNAPOT_SUPPORTED = 0; localparam SVINVAL_SUPPORTED = 0; +localparam ZAAMO_SUPPORTED = 0; +localparam ZALRSC_SUPPORTED = 0; // LSU microarchitectural Features localparam BUS_SUPPORTED = 1; diff --git a/config/rv32gc/config.vh b/config/rv32gc/config.vh index d6fb995b1..8c63d24ff 100644 --- a/config/rv32gc/config.vh +++ b/config/rv32gc/config.vh @@ -52,6 +52,8 @@ localparam ZICOND_SUPPORTED = 1; localparam SVPBMT_SUPPORTED = 0; localparam SVNAPOT_SUPPORTED = 0; localparam SVINVAL_SUPPORTED = 1; +localparam ZAAMO_SUPPORTED = 0; +localparam ZALRSC_SUPPORTED = 0; // LSU microarchitectural Features localparam BUS_SUPPORTED = 1; diff --git a/config/rv32i/config.vh b/config/rv32i/config.vh index 490937558..0629461d5 100644 --- a/config/rv32i/config.vh +++ b/config/rv32i/config.vh @@ -51,6 +51,8 @@ localparam ZICOND_SUPPORTED = 0; localparam SVPBMT_SUPPORTED = 0; localparam SVNAPOT_SUPPORTED = 0; localparam SVINVAL_SUPPORTED = 0; +localparam ZAAMO_SUPPORTED = 0; +localparam ZALRSC_SUPPORTED = 0; // LSU microarchitectural Features localparam BUS_SUPPORTED = 0; diff --git a/config/rv32imc/config.vh b/config/rv32imc/config.vh index 357eba840..40b46308f 100644 --- a/config/rv32imc/config.vh +++ b/config/rv32imc/config.vh @@ -50,6 +50,8 @@ localparam ZICOND_SUPPORTED = 0; localparam SVPBMT_SUPPORTED = 0; localparam SVNAPOT_SUPPORTED = 0; localparam SVINVAL_SUPPORTED = 0; +localparam ZAAMO_SUPPORTED = 0; +localparam ZALRSC_SUPPORTED = 0; // LSU microarchitectural Features localparam BUS_SUPPORTED = 1; diff --git a/config/rv64gc/config.vh b/config/rv64gc/config.vh index 1d6c5e9f4..b82b3cd5d 100644 --- a/config/rv64gc/config.vh +++ b/config/rv64gc/config.vh @@ -51,6 +51,8 @@ localparam ZICOND_SUPPORTED = 1; localparam SVPBMT_SUPPORTED = 1; localparam SVNAPOT_SUPPORTED = 1; localparam SVINVAL_SUPPORTED = 1; +localparam ZAAMO_SUPPORTED = 0; +localparam ZALRSC_SUPPORTED = 0; // LSU microarchitectural Features localparam BUS_SUPPORTED = 1; diff --git a/config/rv64i/config.vh b/config/rv64i/config.vh index a289003cc..4625d3718 100644 --- a/config/rv64i/config.vh +++ b/config/rv64i/config.vh @@ -51,6 +51,8 @@ localparam ZICOND_SUPPORTED = 0; localparam SVPBMT_SUPPORTED = 0; localparam SVNAPOT_SUPPORTED = 0; localparam SVINVAL_SUPPORTED = 0; +localparam ZAAMO_SUPPORTED = 0; +localparam ZALRSC_SUPPORTED = 0; // LSU microarchitectural Features localparam BUS_SUPPORTED = 0; diff --git a/config/shared/parameter-defs.vh b/config/shared/parameter-defs.vh index 5635b286c..1aa6da5d3 100644 --- a/config/shared/parameter-defs.vh +++ b/config/shared/parameter-defs.vh @@ -31,6 +31,8 @@ localparam cvw_t P = '{ SVPBMT_SUPPORTED : SVPBMT_SUPPORTED, SVNAPOT_SUPPORTED : SVNAPOT_SUPPORTED, SVINVAL_SUPPORTED : SVINVAL_SUPPORTED, + ZAAMO_SUPPORTED : ZAAMO_SUPPORTED, + ZALRSC_SUPPORTED : ZALRSC_SUPPORTED, BUS_SUPPORTED : BUS_SUPPORTED, DCACHE_SUPPORTED : DCACHE_SUPPORTED, ICACHE_SUPPORTED : ICACHE_SUPPORTED, diff --git a/src/cvw.sv b/src/cvw.sv index 75ff3f7e7..cba95c0fa 100644 --- a/src/cvw.sv +++ b/src/cvw.sv @@ -66,6 +66,8 @@ typedef struct packed { logic SVPBMT_SUPPORTED; logic SVNAPOT_SUPPORTED; logic SVINVAL_SUPPORTED; + logic ZAAMO_SUPPORTED; + logic ZALRSC_SUPPORTED; // Microarchitectural Features logic BUS_SUPPORTED; diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index 45dd92e98..005baa56b 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -265,12 +265,12 @@ module controller import cvw::*; #(parameter cvw_t P) ( ControlsD = `CTRLW'b0_001_01_01_000_0_0_0_0_0_0_0_0_0_00_0_0; // stores 7'b0100111: if (FLSFunctD) ControlsD = `CTRLW'b0_001_01_01_000_0_0_0_0_0_0_0_0_0_00_0_1; // fsw - only legal if FP supported - 7'b0101111: if (P.A_SUPPORTED & AFunctD) begin - if (InstrD[31:27] == 5'b00010 & Rs2D == 5'b0) + 7'b0101111: if (AFunctD) begin + if ((P.A_SUPPORTED | P.ZALRSC_SUPPORTED) & InstrD[31:27] == 5'b00010 & Rs2D == 5'b0) ControlsD = `CTRLW'b1_000_00_10_001_0_0_0_0_0_0_0_0_0_01_0_0; // lr - else if (InstrD[31:27] == 5'b00011) + else if ((P.A_SUPPORTED | P.ZALRSC_SUPPORTED) & InstrD[31:27] == 5'b00011) ControlsD = `CTRLW'b1_101_01_01_100_0_0_0_0_0_0_0_0_0_01_0_0; // sc - else if (AMOFunctD) + else if ((P.A_SUPPORTED | P.ZAAMO_SUPPORTED) & AMOFunctD) ControlsD = `CTRLW'b1_101_01_11_001_0_0_0_0_0_0_0_0_0_10_0_0; // amo end 7'b0110011: if (RFunctD) diff --git a/src/ieu/datapath.sv b/src/ieu/datapath.sv index de3e46b03..30848ea6d 100644 --- a/src/ieu/datapath.sv +++ b/src/ieu/datapath.sv @@ -139,6 +139,6 @@ module datapath import cvw::*; #(parameter cvw_t P) ( mux5 #(P.XLEN) resultmuxW(IFCvtResultW, ReadDataW, CSRReadValW, MulDivResultW, SCResultW, ResultSrcW, ResultW); // handle Store Conditional result if atomic extension supported - if (P.A_SUPPORTED) assign SCResultW = {{(P.XLEN-1){1'b0}}, SquashSCW}; - else assign SCResultW = '0; + if (P.A_SUPPORTED | P.ZALRSC_SUPPORTED) assign SCResultW = {{(P.XLEN-1){1'b0}}, SquashSCW}; + else assign SCResultW = '0; endmodule diff --git a/src/lsu/atomic.sv b/src/lsu/atomic.sv index 7dbd0c8a2..704eb4c62 100644 --- a/src/lsu/atomic.sv +++ b/src/lsu/atomic.sv @@ -48,11 +48,20 @@ module atomic import cvw::*; #(parameter cvw_t P) ( logic [P.XLEN-1:0] AMOResultM; logic MemReadM; - amoalu #(P) amoalu(.ReadDataM, .IHWriteDataM, .LSUFunct7M, .LSUFunct3M, .AMOResultM); - - mux2 #(P.XLEN) wdmux(IHWriteDataM, AMOResultM, LSUAtomicM[1], IMAWriteDataM); - assign MemReadM = PreLSURWM[1] & ~IgnoreRequest; - - lrsc #(P) lrsc(.clk, .reset, .StallW, .MemReadM, .PreLSURWM, .LSUAtomicM, .PAdrM, .SquashSCW, .LSURWM); + // AMO ALU + if (P.A_SUPPORTED | P.ZAAMO_SUPPORTED) begin + amoalu #(P) amoalu(.ReadDataM, .IHWriteDataM, .LSUFunct7M, .LSUFunct3M, .AMOResultM); + mux2 #(P.XLEN) wdmux(IHWriteDataM, AMOResultM, LSUAtomicM[1], IMAWriteDataM); + end else + assign IMAWriteDataM = IHWriteDataM; + + // LRSC unit + if (P.A_SUPPORTED | P.ZALRSC_SUPPORTED) begin + assign MemReadM = PreLSURWM[1] & ~IgnoreRequest; + lrsc #(P) lrsc(.clk, .reset, .StallW, .MemReadM, .PreLSURWM, .LSUAtomicM, .PAdrM, .SquashSCW, .LSURWM); + end else begin + assign SquashSCW = 0; + assign LSURWM = PreLSURWM; + end endmodule diff --git a/src/lsu/lsu.sv b/src/lsu/lsu.sv index cb9cd0722..31441a095 100644 --- a/src/lsu/lsu.sv +++ b/src/lsu/lsu.sv @@ -397,7 +397,7 @@ module lsu import cvw::*; #(parameter cvw_t P) ( // Atomic operations ///////////////////////////////////////////////////////////////////////////////////////////// - if (P.A_SUPPORTED) begin:atomic + if (P.A_SUPPORTED | P.ZAAMO_SUPPORTED | P.ZALRSC_SUPPORTED) begin:atomic atomic #(P) atomic(.clk, .reset, .StallW, .ReadDataM(ReadDataM[P.XLEN-1:0]), .IHWriteDataM, .PAdrM, .LSUFunct7M, .LSUFunct3M, .LSUAtomicM, .PreLSURWM, .IgnoreRequest, .IMAWriteDataM, .SquashSCW, .LSURWM); diff --git a/testbench/common/riscvassertions.sv b/testbench/common/riscvassertions.sv index 3f50d3f7c..84b7531a8 100644 --- a/testbench/common/riscvassertions.sv +++ b/testbench/common/riscvassertions.sv @@ -67,6 +67,7 @@ module riscvassertions import cvw::*; #(parameter cvw_t P); assert ((P.ZCF_SUPPORTED == 0) || (P.F_SUPPORTED == 1)) else $fatal(1, "ZCF requires F"); assert ((P.ZCD_SUPPORTED == 0) || (P.D_SUPPORTED == 1)) else $fatal(1, "ZCD requires D"); assert ((P.LLEN == P.XLEN) || (P.DCACHE_SUPPORTED)) else $fatal(1, "LLEN > XLEN (D on RV32 or Q on RV64) requires data cache"); + assert (P.A_SUPPORTED + P.ZAAMO_SUPPORTED + P.ZALRSC_SUPPORTED < 2) else $fatal(1, "At most one of A, Zaamo, or Zalrsc can be supported"); end endmodule