More fround stub code to keep VCS happy

bin/regression-wally

@@ -274,6 +274,7 @@ os.chdir(regressionDir)
 
 coveragesim = "questa"  # Questa is required for code/functional coverage
 defaultsim = "questa"   # Default simulator for all other tests; change to Verilator when flow is ready
+#defaultsim = "verilator"   # Default simulator for all other tests
 
 coverage = '--coverage' in sys.argv
 fp = '--fp' in sys.argv
@@ -300,9 +301,9 @@ configs = [
     TestCase(
         name="lints",
         variant="all",
-        cmd="lint-wally " + nightMode + " | tee " + WALLY + "/sim/questa/logs/all_lints.log",
+        cmd="lint-wally " + nightMode + " | tee " + WALLY + "/sim/verilator/logs/all_lints.log",
         grepstr="lints run with no errors or warnings",
-        grepfile = WALLY + "/sim/questa/logs/all_lints.log")
+        grepfile = WALLY + "/sim/verilator/logs/all_lints.log")
     ]
 
 if (coverage):  # only run RV64GC tests on Questa in coverage mode

src/fpu/fpu.sv

@@ -162,7 +162,9 @@ module fpu import cvw::*;  #(parameter cvw_t P) (
   logic                        StallUnpackedM;                     // Stall unpacker outputs during multicycle fdivsqrt
   logic [P.FLEN-1:0]           SgnExtXE;                           // Sign-extended X input for move to integer
   logic                        mvsgn;                              // sign bit for extending move
-  logic [P.FLEN-1:0]           FliResE;                            // Floating-point load immediate value
+  logic [P.FLEN-1:0]           FliResE;                            // Zfa Floating-point load immediate value
+  logic [P.FLEN-1:0]           FRoundE;                            // Zfa fround output
+  logic [4:0]                  FRoundFlagsE;                       // Zfa fround flags
 
   //////////////////////////////////////////////////////////////////////////////////////////
   // Decode Stage: fctrl decoder, read register file
@@ -267,15 +269,25 @@ module fpu import cvw::*;  #(parameter cvw_t P) (
     .ToInt(FWriteIntE), .XZero(XZeroE), .Fmt(FmtE), .Ce(CeE), .ShiftAmt(CvtShiftAmtE), 
     .ResSubnormUf(CvtResSubnormUfE), .Cs(CsE), .IntZero(IntZeroE), .LzcIn(CvtLzcInE));
 
-  // floating-point load immediate: fli
+  // ZFA: fround and floating-point load immediate fli
   if (P.ZFA_SUPPORTED) begin
     logic [4:0] Rs1E;
     logic [1:0] Fmt2E; // Two-bit format field from instruction
 
+    // fround
+    fround #(P) fround(.Xs(XsE), .Xe(XeE), .Xm(XmE), 
+                       .XNaN(XNaNE), .XSNaN(XSNaNE), .XZero(XZeroE), .Fmt(FmtE), 
+                       .FRound(FRoundE), .FRoundFlags(FRoundFlagsE));
+
+    // fli
     flopenrc #(5) Rs1EReg(clk, reset, FlushE, ~StallE, InstrD[19:15], Rs1E);
     flopenrc #(2) Fmt2EReg(clk, reset, FlushE, ~StallE, InstrD[26:25], Fmt2E);
     fli #(P) fli(.Rs1(Rs1E), .Fmt(Fmt2E), .Imm(FliResE)); 
-  end else assign FliResE = '0;
+  end else begin
+    assign FRoundE = '0; 
+    assign FRoundFlagsE = '0;
+    assign FliResE = '0;
+  end
 
   // fmv.*.x: NaN Box SrcA to extend integer to requested FP size 
   if(P.FPSIZES == 1) 

src/fpu/fround.sv

@@ -34,10 +34,11 @@ module fround import cvw::*;  #(parameter cvw_t P) (
   input  logic                    XNaN,         // X is NaN
   input  logic                    XSNaN,        // X is Signalling NaN
   input  logic                    XZero,        // X is Zero
-  input  logic [P.FMTBITS-1:0]    Fmt          // the input's precision (11=quad 01=double 00=single 10=half)
+  input  logic [P.FMTBITS-1:0]    Fmt,          // the input's precision (11=quad 01=double 00=single 10=half)
+  output logic [P.FLEN-1:0]       FRound,       // Rounded result
+  output logic [4:0]              FRoundFlags   // Rounder flags
 );
 
- 
   logic [P.NE-2:0] Bias;
   logic [P.NE-1:0] E;
   logic [P.NF:0] Imask, Tmasknonneg, Tmaskneg, Tmask, HotE, HotEP1, Trunc, Rnd;
@@ -171,4 +172,7 @@ module fround import cvw::*;  #(parameter cvw_t P) (
   assign Inexact = FRoundNX & ~(XNaN | Exact) & (Rp | T'); 
  */
 
+  assign FRound = '0;
+  assign FRoundFlags = '0;
+
 endmodule