diff --git a/pipelined/src/fpu/fclassify.sv b/pipelined/src/fpu/fclassify.sv
index 9a6b43073..68cdfcedb 100644
--- a/pipelined/src/fpu/fclassify.sv
+++ b/pipelined/src/fpu/fclassify.sv
@@ -6,6 +6,8 @@
 //
 // Purpose: Floating-point classify unit
 // 
+// Documentation: RISC-V System on Chip Design Chapter 13
+//
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
diff --git a/pipelined/src/fpu/fcmp.sv b/pipelined/src/fpu/fcmp.sv
index 758b589e3..e749e9576 100755
--- a/pipelined/src/fpu/fcmp.sv
+++ b/pipelined/src/fpu/fcmp.sv
@@ -7,6 +7,8 @@
 //
 // Purpose: Floating-point comparison unit
 // 
+// Documentation: RISC-V System on Chip Design Chapter 13
+//
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
diff --git a/pipelined/src/fpu/fctrl.sv b/pipelined/src/fpu/fctrl.sv
index b8bb29638..563206134 100755
--- a/pipelined/src/fpu/fctrl.sv
+++ b/pipelined/src/fpu/fctrl.sv
@@ -6,6 +6,8 @@
 //
 // Purpose: floating-point control unit
 // 
+// Documentation: RISC-V System on Chip Design Chapter 13
+//
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
diff --git a/pipelined/src/fpu/fcvt.sv b/pipelined/src/fpu/fcvt.sv
index 41ba1badd..e70947526 100644
--- a/pipelined/src/fpu/fcvt.sv
+++ b/pipelined/src/fpu/fcvt.sv
@@ -7,6 +7,8 @@
 //
 // Purpose: Floating point conversions of configurable size
 // 
+// Documentation: RISC-V System on Chip Design Chapter 13
+//
 // Int component of the Wally configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrt.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrt.sv
index 2fecf769f..c69618f43 100644
--- a/pipelined/src/fpu/fdivsqrt/fdivsqrt.sv
+++ b/pipelined/src/fpu/fdivsqrt/fdivsqrt.sv
@@ -6,6 +6,8 @@
 //
 // Purpose: Combined Divide and Square Root Floating Point and Integer Unit
 // 
+// Documentation: RISC-V System on Chip Design Chapter 13
+//
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtexpcalc.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtexpcalc.sv
index b78f3f537..07cffa268 100644
--- a/pipelined/src/fpu/fdivsqrt/fdivsqrtexpcalc.sv
+++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtexpcalc.sv
@@ -4,8 +4,10 @@
 // Written: David_Harris@hmc.edu, me@KatherineParry.com, cturek@hmc.edu
 // Modified:13 January 2022
 //
-// Purpose: Combined Divide and Square Root Floating Point and Integer Unit
+// Purpose: Exponent caclulation for divide and square root
 // 
+// Documentation: RISC-V System on Chip Design Chapter 13
+//
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtfgen2.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtfgen2.sv
index ae642890e..9c13a91da 100644
--- a/pipelined/src/fpu/fdivsqrt/fdivsqrtfgen2.sv
+++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtfgen2.sv
@@ -6,6 +6,8 @@
 //
 // Purpose: Radix 2 F Addend Generator
 // 
+// Documentation: RISC-V System on Chip Design Chapter 13
+//
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtfgen4.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtfgen4.sv
index 4572ba94d..975d58ebd 100644
--- a/pipelined/src/fpu/fdivsqrt/fdivsqrtfgen4.sv
+++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtfgen4.sv
@@ -6,6 +6,8 @@
 //
 // Purpose: Radix 4 F Addend Generator
 // 
+// Documentation: RISC-V System on Chip Design Chapter 13
+//
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtfsm.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtfsm.sv
index 476a7c904..81f6a5eed 100644
--- a/pipelined/src/fpu/fdivsqrt/fdivsqrtfsm.sv
+++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtfsm.sv
@@ -4,8 +4,10 @@
 // Written: David_Harris@hmc.edu, me@KatherineParry.com, cturek@hmc.edu
 // Modified:13 January 2022
 //
-// Purpose: Combined Divide and Square Root Floating Point and Integer Unit
+// Purpose: divsqrt state machine for multi-cycle operations
 // 
+// Documentation: RISC-V System on Chip Design Chapter 13
+//
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtiter.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtiter.sv
index 9a50679a6..d1cf24354 100644
--- a/pipelined/src/fpu/fdivsqrt/fdivsqrtiter.sv
+++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtiter.sv
@@ -4,8 +4,10 @@
 // Written: David_Harris@hmc.edu, me@KatherineParry.com, cturek@hmc.edu 
 // Modified:13 January 2022
 //
-// Purpose: Combined Divide and Square Root Floating Point and Integer Unit
+// Purpose: k stages of divsqrt logic, plus registers
 // 
+// Documentation: RISC-V System on Chip Design Chapter 13
+//
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv
index 94b7c043f..44b269355 100644
--- a/pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv
+++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv
@@ -4,8 +4,10 @@
 // Written: David_Harris@hmc.edu, me@KatherineParry.com, cturek@hmc.edu
 // Modified:13 January 2022
 //
-// Purpose: Combined Divide and Square Root Floating Point and Integer Unit
+// Purpose: Divide/Square root postprocessing
 // 
+// Documentation: RISC-V System on Chip Design Chapter 13
+//
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv
index 83d3c09de..5d490df28 100644
--- a/pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv
+++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv
@@ -4,8 +4,10 @@
 // Written: David_Harris@hmc.edu, me@KatherineParry.com, cturek@hmc.edu
 // Modified:13 January 2022
 //
-// Purpose: Combined Divide and Square Root Floating Point and Integer Unit
+// Purpose: Divide/Square root preprocessing: integer absolute value and W64, normalization shift
 // 
+// Documentation: RISC-V System on Chip Design Chapter 13
+//
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtqsel2.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtqsel2.sv
index 316e885b8..f18b31f1b 100644
--- a/pipelined/src/fpu/fdivsqrt/fdivsqrtqsel2.sv
+++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtqsel2.sv
@@ -6,6 +6,8 @@
 //
 // Purpose: Radix 2 Quotient Digit Selection
 // 
+// Documentation: RISC-V System on Chip Design Chapter 13
+//
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtqsel4.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtqsel4.sv
index ee5e63a24..3a8a110f0 100644
--- a/pipelined/src/fpu/fdivsqrt/fdivsqrtqsel4.sv
+++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtqsel4.sv
@@ -6,6 +6,8 @@
 //
 // Purpose: Radix 4 Quotient Digit Selection
 // 
+// Documentation: RISC-V System on Chip Design Chapter 13
+//
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtqsel4cmp.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtqsel4cmp.sv
index 104884fc4..882458106 100644
--- a/pipelined/src/fpu/fdivsqrt/fdivsqrtqsel4cmp.sv
+++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtqsel4cmp.sv
@@ -6,6 +6,8 @@
 //
 // Purpose: Comparator-based Radix 4 Quotient Digit Selection
 // 
+// Documentation: RISC-V System on Chip Design Chapter 13
+//
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtstage2.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtstage2.sv
index 48d34972e..63ab6c059 100644
--- a/pipelined/src/fpu/fdivsqrt/fdivsqrtstage2.sv
+++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtstage2.sv
@@ -4,8 +4,10 @@
 // Written: David_Harris@hmc.edu, me@KatherineParry.com, cturek@hmc.edu
 // Modified:13 January 2022
 //
-// Purpose: Combined Divide and Square Root Floating Point and Integer Unit stage
+// Purpose: radix-2 divsqrt recurrence stage
 // 
+// Documentation: RISC-V System on Chip Design Chapter 13
+//
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtstage4.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtstage4.sv
index 93e809ae1..007dd18bb 100644
--- a/pipelined/src/fpu/fdivsqrt/fdivsqrtstage4.sv
+++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtstage4.sv
@@ -4,8 +4,10 @@
 // Written: David_Harris@hmc.edu, me@KatherineParry.com, cturek@hmc.edu
 // Modified:13 January 2022
 //
-// Purpose: Combined Divide and Square Root Floating Point and Integer Unit stage
+// Purpose: radix-4 divsqrt recurrence stage
 // 
+// Documentation: RISC-V System on Chip Design Chapter 13
+//
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtuotfc2.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtuotfc2.sv
index 46289cd2b..65b8940ac 100644
--- a/pipelined/src/fpu/fdivsqrt/fdivsqrtuotfc2.sv
+++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtuotfc2.sv
@@ -6,6 +6,8 @@
 //
 // Purpose: Radix 2 unified on-the-fly converter
 // 
+// Documentation: RISC-V System on Chip Design Chapter 13
+//
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtuotfc4.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtuotfc4.sv
index 5c2168c21..a1416384b 100644
--- a/pipelined/src/fpu/fdivsqrt/fdivsqrtuotfc4.sv
+++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtuotfc4.sv
@@ -6,6 +6,8 @@
 //
 // Purpose: Radix 4 unified on-the-fly converter
 // 
+// Documentation: RISC-V System on Chip Design Chapter 13
+//
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
diff --git a/pipelined/src/fpu/fhazard.sv b/pipelined/src/fpu/fhazard.sv
index 4ee31f0f6..68c801048 100644
--- a/pipelined/src/fpu/fhazard.sv
+++ b/pipelined/src/fpu/fhazard.sv
@@ -6,6 +6,8 @@
 //
 // Purpose: Determine forwarding, stalls and flushes for the FPU
 // 
+// Documentation: RISC-V System on Chip Design Chapter 13
+//
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
diff --git a/pipelined/src/fpu/fma/fma.sv b/pipelined/src/fpu/fma/fma.sv
index b3e1751c0..b4add41dc 100644
--- a/pipelined/src/fpu/fma/fma.sv
+++ b/pipelined/src/fpu/fma/fma.sv
@@ -6,6 +6,8 @@
 //
 // Purpose: Floating point multiply-accumulate of configurable size
 // 
+// Documentation: RISC-V System on Chip Design Chapter 13 (Figure 13.7, 9)
+//
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
diff --git a/pipelined/src/fpu/fma/fmaadd.sv b/pipelined/src/fpu/fma/fmaadd.sv
index 96d81ed2d..20899cc83 100644
--- a/pipelined/src/fpu/fma/fmaadd.sv
+++ b/pipelined/src/fpu/fma/fmaadd.sv
@@ -6,6 +6,8 @@
 //
 // Purpose: FMA significand adder
 // 
+// Documentation: RISC-V System on Chip Design Chapter 13 (Figure 13.11)
+//
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
diff --git a/pipelined/src/fpu/fma/fmaalign.sv b/pipelined/src/fpu/fma/fmaalign.sv
index 2e1218ce0..0f1764b29 100644
--- a/pipelined/src/fpu/fma/fmaalign.sv
+++ b/pipelined/src/fpu/fma/fmaalign.sv
@@ -7,6 +7,8 @@
 //
 // Purpose: FMA alginment shift
 // 
+// Documentation: RISC-V System on Chip Design Chapter 13 (Table 13.10)
+//
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
diff --git a/pipelined/src/fpu/fma/fmaexpadd.sv b/pipelined/src/fpu/fma/fmaexpadd.sv
index dfee67e1d..dfafa410e 100644
--- a/pipelined/src/fpu/fma/fmaexpadd.sv
+++ b/pipelined/src/fpu/fma/fmaexpadd.sv
@@ -6,6 +6,8 @@
 //
 // Purpose: FMA exponent addition
 // 
+// Documentation: RISC-V System on Chip Design Chapter 13 (Table 13.9)
+//
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
diff --git a/pipelined/src/fpu/fma/fmalza.sv b/pipelined/src/fpu/fma/fmalza.sv
index 90bf1cf1b..0dad87d84 100644
--- a/pipelined/src/fpu/fma/fmalza.sv
+++ b/pipelined/src/fpu/fma/fmalza.sv
@@ -6,6 +6,8 @@
 //
 // Purpose: Leading Zero Anticipator
 // 
+// Documentation: RISC-V System on Chip Design Chapter 13 (Figure 13.14)
+//
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
diff --git a/pipelined/src/fpu/fma/fmamult.sv b/pipelined/src/fpu/fma/fmamult.sv
index 6e3aa442d..62fa5bc11 100644
--- a/pipelined/src/fpu/fma/fmamult.sv
+++ b/pipelined/src/fpu/fma/fmamult.sv
@@ -6,6 +6,8 @@
 //
 // Purpose: FMA Significand Multiplier
 // 
+// Documentation: RISC-V System on Chip Design Chapter 13 (Table 13.7)
+//
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
diff --git a/pipelined/src/fpu/fma/fmasign.sv b/pipelined/src/fpu/fma/fmasign.sv
index a73e86216..2bf0ee660 100644
--- a/pipelined/src/fpu/fma/fmasign.sv
+++ b/pipelined/src/fpu/fma/fmasign.sv
@@ -6,6 +6,8 @@
 //
 // Purpose: FMA Sign Logic
 // 
+// Documentation: RISC-V System on Chip Design Chapter 13 (Table 13.8)
+//
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
diff --git a/pipelined/src/fpu/fpu.sv b/pipelined/src/fpu/fpu.sv
index 49d1b982b..66e97f54f 100755
--- a/pipelined/src/fpu/fpu.sv
+++ b/pipelined/src/fpu/fpu.sv
@@ -6,6 +6,8 @@
 //
 // Purpose: Floating Point Unit Top-Level Interface
 // 
+// Documentation: RISC-V System on Chip Design Chapter 13
+//
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
diff --git a/pipelined/src/fpu/fregfile.sv b/pipelined/src/fpu/fregfile.sv
index 282e581e2..1a5a2eecf 100644
--- a/pipelined/src/fpu/fregfile.sv
+++ b/pipelined/src/fpu/fregfile.sv
@@ -6,6 +6,8 @@
 //
 // Purpose: 3R1W 4-port register file for FPU
 // 
+// Documentation: RISC-V System on Chip Design Chapter 13
+//
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
diff --git a/pipelined/src/fpu/fsgninj.sv b/pipelined/src/fpu/fsgninj.sv
index cd425ee72..0348426a2 100755
--- a/pipelined/src/fpu/fsgninj.sv
+++ b/pipelined/src/fpu/fsgninj.sv
@@ -6,6 +6,8 @@
 //
 // Purpose: FPU Sign Injection instructions
 // 
+// Documentation: RISC-V System on Chip Design Chapter 13
+//
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
diff --git a/pipelined/src/fpu/postproc/cvtshiftcalc.sv b/pipelined/src/fpu/postproc/cvtshiftcalc.sv
index 5fbe2882e..6c7516fa3 100644
--- a/pipelined/src/fpu/postproc/cvtshiftcalc.sv
+++ b/pipelined/src/fpu/postproc/cvtshiftcalc.sv
@@ -6,6 +6,8 @@
 //
 // Purpose: Conversion shift calculation
 // 
+// Documentation: RISC-V System on Chip Design Chapter 13
+//
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
diff --git a/pipelined/src/fpu/postproc/divshiftcalc.sv b/pipelined/src/fpu/postproc/divshiftcalc.sv
index 27db564ce..a8f00b46f 100644
--- a/pipelined/src/fpu/postproc/divshiftcalc.sv
+++ b/pipelined/src/fpu/postproc/divshiftcalc.sv
@@ -6,6 +6,8 @@
 //
 // Purpose: Division shift calculation
 // 
+// Documentation: RISC-V System on Chip Design Chapter 13
+//
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
diff --git a/pipelined/src/fpu/postproc/flags.sv b/pipelined/src/fpu/postproc/flags.sv
index 6ec601db0..c1dcab858 100644
--- a/pipelined/src/fpu/postproc/flags.sv
+++ b/pipelined/src/fpu/postproc/flags.sv
@@ -6,6 +6,8 @@
 //
 // Purpose: Post-Processing flag calculation
 // 
+// Documentation: RISC-V System on Chip Design Chapter 13
+//
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
diff --git a/pipelined/src/fpu/postproc/fmashiftcalc.sv b/pipelined/src/fpu/postproc/fmashiftcalc.sv
index 79dc1f0dd..f861d9162 100644
--- a/pipelined/src/fpu/postproc/fmashiftcalc.sv
+++ b/pipelined/src/fpu/postproc/fmashiftcalc.sv
@@ -6,6 +6,8 @@
 //
 // Purpose: FMA shift calculation
 // 
+// Documentation: RISC-V System on Chip Design Chapter 13
+//
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
diff --git a/pipelined/src/fpu/postproc/negateintres.sv b/pipelined/src/fpu/postproc/negateintres.sv
index 596ddb308..5b7e7cbfd 100644
--- a/pipelined/src/fpu/postproc/negateintres.sv
+++ b/pipelined/src/fpu/postproc/negateintres.sv
@@ -6,6 +6,8 @@
 //
 // Purpose: Negate integer result
 // 
+// Documentation: RISC-V System on Chip Design Chapter 13
+//
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
diff --git a/pipelined/src/fpu/postproc/normshift.sv b/pipelined/src/fpu/postproc/normshift.sv
index d48e97582..8c4405962 100644
--- a/pipelined/src/fpu/postproc/normshift.sv
+++ b/pipelined/src/fpu/postproc/normshift.sv
@@ -6,6 +6,8 @@
 //
 // Purpose: normalization shifter
 // 
+// Documentation: RISC-V System on Chip Design Chapter 13
+//
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
diff --git a/pipelined/src/fpu/postproc/postprocess.sv b/pipelined/src/fpu/postproc/postprocess.sv
index 3906ad57a..f15214457 100644
--- a/pipelined/src/fpu/postproc/postprocess.sv
+++ b/pipelined/src/fpu/postproc/postprocess.sv
@@ -4,8 +4,10 @@
 // Written: me@KatherineParry.com
 // Modified: 7/5/2022
 //
-// Purpose: Post-Processing
+// Purpose: Post-Processing: normalization, rounding, sign, flags, special cases
 // 
+// Documentation: RISC-V System on Chip Design Chapter 13
+//
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
diff --git a/pipelined/src/fpu/postproc/resultsign.sv b/pipelined/src/fpu/postproc/resultsign.sv
index 7ecf3eb66..2ac0ae3c0 100644
--- a/pipelined/src/fpu/postproc/resultsign.sv
+++ b/pipelined/src/fpu/postproc/resultsign.sv
@@ -6,6 +6,8 @@
 //
 // Purpose: calculating the result's sign
 // 
+// Documentation: RISC-V System on Chip Design Chapter 13
+//
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
diff --git a/pipelined/src/fpu/postproc/round.sv b/pipelined/src/fpu/postproc/round.sv
index 62b7d92b7..820b1a92d 100644
--- a/pipelined/src/fpu/postproc/round.sv
+++ b/pipelined/src/fpu/postproc/round.sv
@@ -6,6 +6,8 @@
 //
 // Purpose: Rounder
 // 
+// Documentation: RISC-V System on Chip Design Chapter 13
+//
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
diff --git a/pipelined/src/fpu/postproc/roundsign.sv b/pipelined/src/fpu/postproc/roundsign.sv
index e768332aa..40231ecd3 100644
--- a/pipelined/src/fpu/postproc/roundsign.sv
+++ b/pipelined/src/fpu/postproc/roundsign.sv
@@ -6,6 +6,8 @@
 //
 // Purpose: Sign calculation for rounding
 // 
+// Documentation: RISC-V System on Chip Design Chapter 13
+//
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
diff --git a/pipelined/src/fpu/postproc/shiftcorrection.sv b/pipelined/src/fpu/postproc/shiftcorrection.sv
index 602e72e72..a86facbcd 100644
--- a/pipelined/src/fpu/postproc/shiftcorrection.sv
+++ b/pipelined/src/fpu/postproc/shiftcorrection.sv
@@ -6,6 +6,8 @@
 //
 // Purpose: shift correction
 // 
+// Documentation: RISC-V System on Chip Design Chapter 13
+//
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
diff --git a/pipelined/src/fpu/postproc/specialcase.sv b/pipelined/src/fpu/postproc/specialcase.sv
index 9c9663c9c..f87c42f02 100644
--- a/pipelined/src/fpu/postproc/specialcase.sv
+++ b/pipelined/src/fpu/postproc/specialcase.sv
@@ -6,6 +6,8 @@
 //
 // Purpose: special case selection
 // 
+// Documentation: RISC-V System on Chip Design Chapter 13
+//
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
diff --git a/pipelined/src/fpu/unpack.sv b/pipelined/src/fpu/unpack.sv
index 47eb4fb65..8e6ba2559 100644
--- a/pipelined/src/fpu/unpack.sv
+++ b/pipelined/src/fpu/unpack.sv
@@ -6,6 +6,8 @@
 //
 // Purpose: unpack X, Y, Z floating-point inputs
 // 
+// Documentation: RISC-V System on Chip Design Chapter 13
+//
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
diff --git a/pipelined/src/fpu/unpackinput.sv b/pipelined/src/fpu/unpackinput.sv
index 2d88eee4d..9d2b0b6ab 100644
--- a/pipelined/src/fpu/unpackinput.sv
+++ b/pipelined/src/fpu/unpackinput.sv
@@ -6,6 +6,8 @@
 //
 // Purpose: unpack input: extract sign, exponent, significand, characteristics
 // 
+// Documentation: RISC-V System on Chip Design Chapter 13
+//
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
diff --git a/pipelined/src/generic/flop/flop.sv b/pipelined/src/generic/flop/flop.sv
index 14b09899b..1e906dca8 100644
--- a/pipelined/src/generic/flop/flop.sv
+++ b/pipelined/src/generic/flop/flop.sv
@@ -4,7 +4,7 @@
 // Written: David_Harris@hmc.edu 9 January 2021
 // Modified: 
 //
-// Purpose: various flavors of flip-flops
+// Purpose: D flip-flop
 // 
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
@@ -26,7 +26,6 @@
 
 `include "wally-config.vh"
 
-// ordinary flip-flop
 module flop #(parameter WIDTH = 8) ( 
   input  logic             clk,
   input  logic [WIDTH-1:0] d, 
diff --git a/pipelined/src/generic/flop/flopen.sv b/pipelined/src/generic/flop/flopen.sv
index 5987222dd..32e0d7dd3 100644
--- a/pipelined/src/generic/flop/flopen.sv
+++ b/pipelined/src/generic/flop/flopen.sv
@@ -4,7 +4,7 @@
 // Written: David_Harris@hmc.edu 9 January 2021
 // Modified: 
 //
-// Purpose: various flavors of flip-flops
+// Purpose: D flip-flop with enable
 // 
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
@@ -26,7 +26,6 @@
 
 `include "wally-config.vh"
 
-// flop with enable
 module flopen #(parameter WIDTH = 8) (
   input  logic             clk, en,
   input  logic [WIDTH-1:0] d, 
diff --git a/pipelined/src/generic/flop/flopenl.sv b/pipelined/src/generic/flop/flopenl.sv
index b01c5b5b6..094779c74 100644
--- a/pipelined/src/generic/flop/flopenl.sv
+++ b/pipelined/src/generic/flop/flopenl.sv
@@ -4,7 +4,7 @@
 // Written: David_Harris@hmc.edu 9 January 2021
 // Modified: 
 //
-// Purpose: various flavors of flip-flops
+// Purpose: D flip-flop with enable and synchronous load
 // 
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
@@ -26,7 +26,6 @@
 
 `include "wally-config.vh"
 
-// flop with enable, synchronous load
 module flopenl #(parameter WIDTH = 8, parameter type TYPE=logic [WIDTH-1:0]) (
   input  logic clk, load, en,
   input  TYPE d,
diff --git a/pipelined/src/generic/flop/flopenr.sv b/pipelined/src/generic/flop/flopenr.sv
index 74cea0cdc..3b8129e40 100644
--- a/pipelined/src/generic/flop/flopenr.sv
+++ b/pipelined/src/generic/flop/flopenr.sv
@@ -4,7 +4,7 @@
 // Written: David_Harris@hmc.edu 9 January 2021
 // Modified: 
 //
-// Purpose: various flavors of flip-flops
+// Purpose: D flip-flop with enable, synchronous reset
 // 
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
@@ -26,7 +26,6 @@
 
 `include "wally-config.vh"
 
-// flop with enable, synchronous reset
 module flopenr #(parameter WIDTH = 8) (
   input  logic             clk, reset, en,
   input  logic [WIDTH-1:0] d, 
diff --git a/pipelined/src/generic/flop/flopenrc.sv b/pipelined/src/generic/flop/flopenrc.sv
index 85fb09bd3..b3d5a1e8e 100644
--- a/pipelined/src/generic/flop/flopenrc.sv
+++ b/pipelined/src/generic/flop/flopenrc.sv
@@ -4,7 +4,7 @@
 // Written: David_Harris@hmc.edu 9 January 2021
 // Modified: 
 //
-// Purpose: various flavors of flip-flops
+// Purpose: D flip-flop with enable, synchronous reset, enabled clear
 // 
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
@@ -26,7 +26,6 @@
 
 `include "wally-config.vh"
 
-// flop with enable, synchronous reset, enabled clear
 module flopenrc #(parameter WIDTH = 8) (
   input  logic             clk, reset, clear, en,
   input  logic [WIDTH-1:0] d, 
diff --git a/pipelined/src/generic/flop/flopens.sv b/pipelined/src/generic/flop/flopens.sv
index 257d28085..1f4c18051 100644
--- a/pipelined/src/generic/flop/flopens.sv
+++ b/pipelined/src/generic/flop/flopens.sv
@@ -4,7 +4,7 @@
 // Written: David_Harris@hmc.edu 9 January 2021
 // Modified: 
 //
-// Purpose: various flavors of flip-flops
+// Purpose: D flip-flop with enable, synchronous set
 // 
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
@@ -26,7 +26,6 @@
 
 `include "wally-config.vh"
 
-// flop with enable, synchronous set
 module flopens #(parameter WIDTH = 8) (
   input  logic             clk, set, en,
   input  logic [WIDTH-1:0] d, 
diff --git a/pipelined/src/generic/flop/flopr.sv b/pipelined/src/generic/flop/flopr.sv
index d3296d926..b2f99b3cd 100644
--- a/pipelined/src/generic/flop/flopr.sv
+++ b/pipelined/src/generic/flop/flopr.sv
@@ -4,7 +4,7 @@
 // Written: David_Harris@hmc.edu 9 January 2021
 // Modified: 
 //
-// Purpose: various flavors of flip-flops
+// Purpose: D flip-flop with synchronous reset
 // 
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
@@ -26,7 +26,6 @@
 
 `include "wally-config.vh"
 
-// flop with synchronous reset
 module flopr #(parameter WIDTH = 8) ( 
   input  logic             clk, reset,
   input  logic [WIDTH-1:0] d, 
diff --git a/pipelined/src/generic/flop/floprc.sv b/pipelined/src/generic/flop/floprc.sv
index 995cff602..8275a8f96 100644
--- a/pipelined/src/generic/flop/floprc.sv
+++ b/pipelined/src/generic/flop/floprc.sv
@@ -4,8 +4,8 @@
 // Written: David_Harris@hmc.edu 9 January 2021
 // Modified: 
 //
-// Purpose: various flavors of flip-flops
-// 
+// Purpose: D flip-flop with synchronous reset and clear
+//
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
@@ -26,7 +26,6 @@
 
 `include "wally-config.vh"
 
-// flop with synchronous reset, synchronous clear
 module floprc #(parameter WIDTH = 8) (
   input  logic clk,
   input  logic reset,
diff --git a/pipelined/src/generic/flop/synchronizer.sv b/pipelined/src/generic/flop/synchronizer.sv
index d5594c99b..f10efaeaf 100644
--- a/pipelined/src/generic/flop/synchronizer.sv
+++ b/pipelined/src/generic/flop/synchronizer.sv
@@ -26,7 +26,6 @@
 
 `include "wally-config.vh"
 
-// ordinary flip-flop
 module synchronizer ( 
   input  logic clk,
   input  logic d, 
diff --git a/pipelined/src/ieu/comparator.sv b/pipelined/src/ieu/comparator.sv
index 27226a6ad..33dbab147 100644
--- a/pipelined/src/ieu/comparator.sv
+++ b/pipelined/src/ieu/comparator.sv
@@ -6,6 +6,8 @@
 //
 // Purpose: Branch comparison
 // 
+// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.7)
+//
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
diff --git a/pipelined/src/ieu/controller.sv b/pipelined/src/ieu/controller.sv
index abc86da68..57b34b1c5 100644
--- a/pipelined/src/ieu/controller.sv
+++ b/pipelined/src/ieu/controller.sv
@@ -6,6 +6,8 @@
 //
 // Purpose: Top level controller module
 // 
+// Documentation: RISC-V System on Chip Design Chapter 4 (Section 4.1.4, Figure 4.8, Table 4.5)
+//
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
diff --git a/pipelined/src/ieu/datapath.sv b/pipelined/src/ieu/datapath.sv
index 0e3e2e81a..4bcd1a60d 100644
--- a/pipelined/src/ieu/datapath.sv
+++ b/pipelined/src/ieu/datapath.sv
@@ -6,6 +6,8 @@
 //
 // Purpose: Wally Integer Datapath
 // 
+// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.12)
+//
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
diff --git a/pipelined/src/ieu/extend.sv b/pipelined/src/ieu/extend.sv
index 74b6acdfd..808358500 100644
--- a/pipelined/src/ieu/extend.sv
+++ b/pipelined/src/ieu/extend.sv
@@ -4,8 +4,10 @@
 // Written: David_Harris@hmc.edu 9 January 2021
 // Modified: 
 //
-// Purpose: 
+// Purpose: Produce sign-extended immediates from various formats
 // 
+// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.3)
+//
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
diff --git a/pipelined/src/ieu/forward.sv b/pipelined/src/ieu/forward.sv
index c76b2355d..8617be826 100644
--- a/pipelined/src/ieu/forward.sv
+++ b/pipelined/src/ieu/forward.sv
@@ -6,6 +6,8 @@
 //
 // Purpose: Determine datapath forwarding
 // 
+// Documentation: RISC-V System on Chip Design Chapter 4 (Section 4.2.2.3)
+//
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
diff --git a/pipelined/src/ieu/ieu.sv b/pipelined/src/ieu/ieu.sv
index 9d6d81d46..ba04aa5e4 100644
--- a/pipelined/src/ieu/ieu.sv
+++ b/pipelined/src/ieu/ieu.sv
@@ -6,6 +6,8 @@
 //
 // Purpose: Integer Execution Unit: datapath and controller
 // 
+// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.12)
+//
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
diff --git a/pipelined/src/ieu/regfile.sv b/pipelined/src/ieu/regfile.sv
index 1680d5bcc..e08c46779 100644
--- a/pipelined/src/ieu/regfile.sv
+++ b/pipelined/src/ieu/regfile.sv
@@ -6,6 +6,8 @@
 //
 // Purpose: 3-port register file
 // 
+// Documentation: RISC-V System on Chip Design Chapter 4
+//
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
diff --git a/pipelined/src/ieu/shifter.sv b/pipelined/src/ieu/shifter.sv
index 015cc7808..c03a40cd9 100644
--- a/pipelined/src/ieu/shifter.sv
+++ b/pipelined/src/ieu/shifter.sv
@@ -6,6 +6,8 @@
 //
 // Purpose: RISC-V 32/64 bit shifter
 // 
+// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.5, Table 4.3)
+//
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
diff --git a/pipelined/src/privileged/csrm.sv b/pipelined/src/privileged/csrm.sv
index d100285cd..8b8718380 100644
--- a/pipelined/src/privileged/csrm.sv
+++ b/pipelined/src/privileged/csrm.sv
@@ -7,7 +7,10 @@
 //
 // Purpose: Machine-Mode Control and Status Registers
 //          See RISC-V Privileged Mode Specification 20190608 
-// 
+// Note: the CSRs do not support the following optional features
+//   - Disabling portions of the instruction set with bits of the MISA register
+//   - Changing from RV64 to RV32 by writing the SXL/UXL bits of the STATUS register
+//
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
 // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
diff --git a/pipelined/src/wally/wallypipelinedsoc.sv b/pipelined/src/wally/wallypipelinedsoc.sv
index 255009474..bb5094cc9 100644
--- a/pipelined/src/wally/wallypipelinedsoc.sv
+++ b/pipelined/src/wally/wallypipelinedsoc.sv
@@ -4,12 +4,7 @@
 // Written: David_Harris@hmc.edu 6 November 2020
 // Modified: 
 //
-// Purpose: System on chip including pipelined processor and memories
-// Full RV32/64IC instruction set
-//
-// Note: the CSRs do not support the following features
-//- Disabling portions of the instruction set with bits of the MISA register
-//- Changing from RV64 to RV32 by writing the SXL/UXL bits of the STATUS register
+// Purpose: System on chip including pipelined processor and uncore memories/peripherals
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // 
@@ -32,35 +27,36 @@
 `include "wally-config.vh"
 
 module wallypipelinedsoc (
-  input  logic 		   clk, reset_ext, 
-  output logic       reset,
+  input  logic 		            clk, 
+  input  logic                reset_ext, 
+  output logic                reset,
   // AHB Interface
-  input  logic [`AHBW-1:0]  HRDATAEXT,
-  input  logic 		   HREADYEXT, HRESPEXT,
-  output logic 		   HSELEXT,
+  input  logic [`AHBW-1:0]    HRDATAEXT,
+  input  logic 		            HREADYEXT, HRESPEXT,
+  output logic 		            HSELEXT,
   // outputs to external memory, shared with uncore memory
-  output logic 		   HCLK, HRESETn,
+  output logic 		            HCLK, HRESETn,
   output logic [`PA_BITS-1:0] HADDR,
-  output logic [`AHBW-1:0] HWDATA,
-  output logic [`XLEN/8-1:0] HWSTRB,
-  output logic 		   HWRITE,
-  output logic [2:0] 	   HSIZE,
-  output logic [2:0] 	   HBURST,
-  output logic [3:0] 	   HPROT,
-  output logic [1:0] 	   HTRANS,
-  output logic 		   HMASTLOCK,
-  output logic 		   HREADY,
+  output logic [`AHBW-1:0]    HWDATA,
+  output logic [`XLEN/8-1:0]  HWSTRB,
+  output logic 		            HWRITE,
+  output logic [2:0] 	        HSIZE,
+  output logic [2:0] 	        HBURST,
+  output logic [3:0] 	        HPROT,
+  output logic [1:0] 	        HTRANS,
+  output logic 		            HMASTLOCK,
+  output logic 		            HREADY,
   // I/O Interface
-  input  logic       TIMECLK,
-  input logic [31:0] 	   GPIOPinsIn,
-  output logic [31:0] 	   GPIOPinsOut, GPIOPinsEn,
-  input logic 		   UARTSin,
-  output logic 		   UARTSout,
-  input logic 		   SDCCmdIn,
-  output logic 		   SDCCmdOut,
-  output logic 		   SDCCmdOE,			  
-  input logic [3:0] 	   SDCDatIn,
-  output logic 		   SDCCLK			  
+  input  logic                TIMECLK,
+  input  logic [31:0] 	        GPIOPinsIn,
+  output logic [31:0] 	      GPIOPinsOut, GPIOPinsEn,
+  input  logic 		            UARTSin,
+  output logic 		            UARTSout,
+  input  logic 		            SDCCmdIn,
+  output logic 		            SDCCmdOut,
+  output logic 		            SDCCmdOE,			  
+  input  logic [3:0] 	        SDCDatIn,
+  output logic 		            SDCCLK			  
 );
 
   // Uncore signals