Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main

pipelined/src/hazard/hazard.sv

@@ -61,6 +61,7 @@ module hazard(
 
   // *** can stalls be pushed into earlier stages (e.g. no stall after Decode?)
 
+  // *** consider replacing CSRWriteFencePendingDEM with a flush rather than a stall.  
   assign StallFCause = CSRWriteFencePendingDEM & ~(TrapM | RetM | BPPredWrongE);
   // stall in decode if instruction is a load/mul/csr dependent on previous
   assign StallDCause = (LoadStallD | StoreStallD | MDUStallD | CSRRdStallD | FPUStallD | FStallD) & ~(TrapM | RetM | BPPredWrongE);    

pipelined/src/ifu/ifu.sv

@@ -249,7 +249,7 @@ module ifu (
       flopen #(`XLEN) fb(.clk, .en(IFUBusRead), .d(HRDATA), .q(AllInstrRawF[31:0]));
 
       busfsm #(LOGBWPL) busfsm(
-        .clk, .reset, .IgnoreRequest(ITLBMissF), .RW(NonIROMMemRWM), 
+        .clk, .reset, .RW(NonIROMMemRWM & ~{ITLBMissF, ITLBMissF}), 
         .BusAck(IFUBusAck), .BusInit(IFUBusInit), .CPUBusy, 
         .BusStall, .BusWrite(), .BusRead(IFUBusRead), 
         .HTRANS(IFUHTRANS), .BusCommitted());

pipelined/src/lsu/busfsm.sv

@@ -35,7 +35,6 @@ module busfsm #(parameter integer LOGWPL)
   (input logic               clk,
    input logic               reset,
 
-   input logic               IgnoreRequest,
    input logic [1:0]         RW,
    input logic               BusAck,
    input logic               BusInit, // This might be better as LSUBusLock, or to send this using BusAck.
@@ -65,30 +64,29 @@ module busfsm #(parameter integer LOGWPL)
   
   always_comb begin
 	case(BusCurrState)
-	  STATE_BUS_READY:                 if(IgnoreRequest)             BusNextState = STATE_BUS_READY;
+	  STATE_BUS_READY:               if(RW[0])                BusNextState = STATE_BUS_UNCACHED_WRITE;
-	                                   else if(RW[0])                BusNextState = STATE_BUS_UNCACHED_WRITE;
+		                             else if(RW[1])                BusNextState = STATE_BUS_UNCACHED_READ;
-		                                 else if(RW[1])                BusNextState = STATE_BUS_UNCACHED_READ;
                                      else                          BusNextState = STATE_BUS_READY;
       STATE_BUS_UNCACHED_WRITE:      if(BusAck)                    BusNextState = STATE_BUS_UNCACHED_WRITE_DONE;
-		                                 else                          BusNextState = STATE_BUS_UNCACHED_WRITE;
+		                             else                          BusNextState = STATE_BUS_UNCACHED_WRITE;
       STATE_BUS_UNCACHED_READ:       if(BusAck)                    BusNextState = STATE_BUS_UNCACHED_READ_DONE;
-		                                 else                          BusNextState = STATE_BUS_UNCACHED_READ;
+		                             else                          BusNextState = STATE_BUS_UNCACHED_READ;
       STATE_BUS_UNCACHED_WRITE_DONE: if(CPUBusy)                   BusNextState = STATE_BUS_CPU_BUSY;
                                      else                          BusNextState = STATE_BUS_READY;
       STATE_BUS_UNCACHED_READ_DONE:  if(CPUBusy)                   BusNextState = STATE_BUS_CPU_BUSY;
                                      else                          BusNextState = STATE_BUS_READY;
-	  STATE_BUS_CPU_BUSY:              if(CPUBusy)                   BusNextState = STATE_BUS_CPU_BUSY;
+	  STATE_BUS_CPU_BUSY:            if(CPUBusy)                   BusNextState = STATE_BUS_CPU_BUSY;
                                      else                          BusNextState = STATE_BUS_READY;
-	  default:                                                       BusNextState = STATE_BUS_READY;
+	  default:                                                     BusNextState = STATE_BUS_READY;
 	endcase
   end
 
-  assign BusStall = (BusCurrState == STATE_BUS_READY & ~IgnoreRequest & |RW) |
+  assign BusStall = (BusCurrState == STATE_BUS_READY & |RW) |
 					(BusCurrState == STATE_BUS_UNCACHED_WRITE) |
 					(BusCurrState == STATE_BUS_UNCACHED_READ);
-  assign BusWrite = (BusCurrState == STATE_BUS_READY & RW[0] & ~IgnoreRequest) |
+  assign BusWrite = (BusCurrState == STATE_BUS_READY & RW[0]) |
 							   (BusCurrState == STATE_BUS_UNCACHED_WRITE);
-  assign BusRead = (BusCurrState == STATE_BUS_READY & RW[1] & ~IgnoreRequest) |
+  assign BusRead = (BusCurrState == STATE_BUS_READY & RW[1]) |
 							  (BusCurrState == STATE_BUS_UNCACHED_READ);
   assign BusCommitted = BusCurrState != STATE_BUS_READY;
 

pipelined/src/lsu/lsu.sv

@@ -184,6 +184,14 @@ module lsu (
       .PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW);
 
   end else begin
+    // Determine which region of physical memory (if any) is being accessed
+
+    // conditionally move adredecs to here and ifu.
+    // the lsu will output LSUHSel to EBU (need the same for ifu).
+    // The ebu will have a mux to select between LSUHSel, IFUHSel
+    // mux for HWSTRB
+    // adrdecs out of uncore.
+    
     assign {DTLBMissM, LoadAccessFaultM, StoreAmoAccessFaultM, LoadMisalignedFaultM, StoreAmoMisalignedFaultM} = '0;
     assign {LoadPageFaultM, StoreAmoPageFaultM} = '0;
     assign LSUPAdrM = PreLSUPAdrM;
@@ -269,7 +277,7 @@ module lsu (
       assign LSUHWDATA = LSUWriteDataM[`XLEN-1:0];
 
       busfsm #(LOGBWPL) busfsm(
-        .clk, .reset, .IgnoreRequest, .RW(LSURWM), 
+        .clk, .reset, .RW(LSURWM & ~{IgnoreRequest, IgnoreRequest}), 
         .BusAck(LSUBusAck), .BusInit(LSUBusInit), .CPUBusy, 
         .BusStall, .BusWrite(LSUBusWrite), .BusRead(LSUBusRead), 
         .HTRANS(LSUHTRANS), .BusCommitted(BusCommittedM));