From 35d0b759d18cd3686f70fec0fef272dcbadcff9a Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Sun, 28 Aug 2022 21:12:27 -0500
Subject: [PATCH 1/3] Removed ignore request from busfsm.
---
pipelined/src/ifu/ifu.sv | 2 +-
pipelined/src/lsu/busfsm.sv | 20 +++++++++-----------
pipelined/src/lsu/lsu.sv | 2 +-
3 files changed, 11 insertions(+), 13 deletions(-)
diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv
index 2b9cfa440..377e5413e 100644
--- a/pipelined/src/ifu/ifu.sv
+++ b/pipelined/src/ifu/ifu.sv
@@ -249,7 +249,7 @@ module ifu (
flopen #(`XLEN) fb(.clk, .en(IFUBusRead), .d(HRDATA), .q(AllInstrRawF[31:0]));
busfsm #(LOGBWPL) busfsm(
- .clk, .reset, .IgnoreRequest(ITLBMissF), .RW(NonIROMMemRWM),
+ .clk, .reset, .RW(NonIROMMemRWM & ~{ITLBMissF, ITLBMissF}),
.BusAck(IFUBusAck), .BusInit(IFUBusInit), .CPUBusy,
.BusStall, .BusWrite(), .BusRead(IFUBusRead),
.HTRANS(IFUHTRANS), .BusCommitted());
diff --git a/pipelined/src/lsu/busfsm.sv b/pipelined/src/lsu/busfsm.sv
index 2e2d9eda4..6d8352f68 100644
--- a/pipelined/src/lsu/busfsm.sv
+++ b/pipelined/src/lsu/busfsm.sv
@@ -35,7 +35,6 @@ module busfsm #(parameter integer LOGWPL)
(input logic clk,
input logic reset,
- input logic IgnoreRequest,
input logic [1:0] RW,
input logic BusAck,
input logic BusInit, // This might be better as LSUBusLock, or to send this using BusAck.
@@ -65,30 +64,29 @@ module busfsm #(parameter integer LOGWPL)
always_comb begin
case(BusCurrState)
- STATE_BUS_READY: if(IgnoreRequest) BusNextState = STATE_BUS_READY;
- else if(RW[0]) BusNextState = STATE_BUS_UNCACHED_WRITE;
- else if(RW[1]) BusNextState = STATE_BUS_UNCACHED_READ;
+ STATE_BUS_READY: if(RW[0]) BusNextState = STATE_BUS_UNCACHED_WRITE;
+ else if(RW[1]) BusNextState = STATE_BUS_UNCACHED_READ;
else BusNextState = STATE_BUS_READY;
STATE_BUS_UNCACHED_WRITE: if(BusAck) BusNextState = STATE_BUS_UNCACHED_WRITE_DONE;
- else BusNextState = STATE_BUS_UNCACHED_WRITE;
+ else BusNextState = STATE_BUS_UNCACHED_WRITE;
STATE_BUS_UNCACHED_READ: if(BusAck) BusNextState = STATE_BUS_UNCACHED_READ_DONE;
- else BusNextState = STATE_BUS_UNCACHED_READ;
+ else BusNextState = STATE_BUS_UNCACHED_READ;
STATE_BUS_UNCACHED_WRITE_DONE: if(CPUBusy) BusNextState = STATE_BUS_CPU_BUSY;
else BusNextState = STATE_BUS_READY;
STATE_BUS_UNCACHED_READ_DONE: if(CPUBusy) BusNextState = STATE_BUS_CPU_BUSY;
else BusNextState = STATE_BUS_READY;
- STATE_BUS_CPU_BUSY: if(CPUBusy) BusNextState = STATE_BUS_CPU_BUSY;
+ STATE_BUS_CPU_BUSY: if(CPUBusy) BusNextState = STATE_BUS_CPU_BUSY;
else BusNextState = STATE_BUS_READY;
- default: BusNextState = STATE_BUS_READY;
+ default: BusNextState = STATE_BUS_READY;
endcase
end
- assign BusStall = (BusCurrState == STATE_BUS_READY & ~IgnoreRequest & |RW) |
+ assign BusStall = (BusCurrState == STATE_BUS_READY & |RW) |
(BusCurrState == STATE_BUS_UNCACHED_WRITE) |
(BusCurrState == STATE_BUS_UNCACHED_READ);
- assign BusWrite = (BusCurrState == STATE_BUS_READY & RW[0] & ~IgnoreRequest) |
+ assign BusWrite = (BusCurrState == STATE_BUS_READY & RW[0]) |
(BusCurrState == STATE_BUS_UNCACHED_WRITE);
- assign BusRead = (BusCurrState == STATE_BUS_READY & RW[1] & ~IgnoreRequest) |
+ assign BusRead = (BusCurrState == STATE_BUS_READY & RW[1]) |
(BusCurrState == STATE_BUS_UNCACHED_READ);
assign BusCommitted = BusCurrState != STATE_BUS_READY;
diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv
index edc26f694..60768ceca 100644
--- a/pipelined/src/lsu/lsu.sv
+++ b/pipelined/src/lsu/lsu.sv
@@ -269,7 +269,7 @@ module lsu (
assign LSUHWDATA = LSUWriteDataM[`XLEN-1:0];
busfsm #(LOGBWPL) busfsm(
- .clk, .reset, .IgnoreRequest, .RW(LSURWM),
+ .clk, .reset, .RW(LSURWM & ~{IgnoreRequest, IgnoreRequest}),
.BusAck(LSUBusAck), .BusInit(LSUBusInit), .CPUBusy,
.BusStall, .BusWrite(LSUBusWrite), .BusRead(LSUBusRead),
.HTRANS(LSUHTRANS), .BusCommitted(BusCommittedM));
From 9a7c7e8398840e7358a035eb437c37294fe44bf6 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Mon, 29 Aug 2022 09:48:00 -0500
Subject: [PATCH 2/3] Added comments about planned changes.
---
pipelined/src/hazard/hazard.sv | 1 +
pipelined/src/lsu/lsu.sv | 9 +++++++++
2 files changed, 10 insertions(+)
diff --git a/pipelined/src/hazard/hazard.sv b/pipelined/src/hazard/hazard.sv
index ac3fc9d9e..b9a6d9575 100644
--- a/pipelined/src/hazard/hazard.sv
+++ b/pipelined/src/hazard/hazard.sv
@@ -61,6 +61,7 @@ module hazard(
// *** can stalls be pushed into earlier stages (e.g. no stall after Decode?)
+ // *** consider replacing CSRWriteFencePendingDEM with a flush rather than a stall.
assign StallFCause = CSRWriteFencePendingDEM & ~(TrapM | RetM | BPPredWrongE);
// stall in decode if instruction is a load/mul/csr dependent on previous
assign StallDCause = (LoadStallD | StoreStallD | MDUStallD | CSRRdStallD | FPUStallD | FStallD) & ~(TrapM | RetM | BPPredWrongE);
diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv
index 60768ceca..6744fbcd0 100644
--- a/pipelined/src/lsu/lsu.sv
+++ b/pipelined/src/lsu/lsu.sv
@@ -184,6 +184,15 @@ module lsu (
.PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW);
end else begin
+ // Determine which region of physical memory (if any) is being accessed
+ adrdecs adrdecs(.PhysicalAddress(LSUPAdrM), AccessRW, AccessRX, AccessRWX, Size, .SelRegions(LSUHSel));
+
+ // conditionally move adredecs to here and ifu.
+ // the lsu will output LSUHSel to EBU (need the same for ifu).
+ // The ebu will have a mux to select between LSUHSel, IFUHSel
+ // mux for HWSTRB
+ // adrdecs out of uncore.
+
assign {DTLBMissM, LoadAccessFaultM, StoreAmoAccessFaultM, LoadMisalignedFaultM, StoreAmoMisalignedFaultM} = '0;
assign {LoadPageFaultM, StoreAmoPageFaultM} = '0;
assign LSUPAdrM = PreLSUPAdrM;
From 40cf4a9ea9385007fafe486ab7f8b6b38dea80bd Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Mon, 29 Aug 2022 11:40:35 -0500
Subject: [PATCH 3/3] Typo.
---
pipelined/src/lsu/lsu.sv | 1 -
1 file changed, 1 deletion(-)
diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv
index 6744fbcd0..713c793d4 100644
--- a/pipelined/src/lsu/lsu.sv
+++ b/pipelined/src/lsu/lsu.sv
@@ -185,7 +185,6 @@ module lsu (
end else begin
// Determine which region of physical memory (if any) is being accessed
- adrdecs adrdecs(.PhysicalAddress(LSUPAdrM), AccessRW, AccessRX, AccessRWX, Size, .SelRegions(LSUHSel));
// conditionally move adredecs to here and ifu.
// the lsu will output LSUHSel to EBU (need the same for ifu).