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Added icache access and icache miss to performance counters.

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This commit is contained in:
Ross Thompson 2022-01-09 22:56:56 -06:00
parent 04ea93aa27
commit 73c488914f
8 changed files with 31 additions and 103 deletions
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78
pipelined/regression/wally-coremark.do
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@ -37,82 +37,8 @@ vsim workopt
mem load -startaddress 268435456 -endaddress 268566527 -filltype value -fillradix hex -filldata 0 /testbench/dut/uncore/ram/ram/RAM mem load -startaddress 268435456 -endaddress 268566527 -filltype value -fillradix hex -filldata 0 /testbench/dut/uncore/ram/ram/RAM
view wave
-- display input and output signals as hexidecimal values do wave.do
# Diplays All Signals recursively
add wave /testbench/clk
add wave /testbench/reset
add wave -divider
#add wave /testbench/dut/hart/ebu/IReadF
#add wave /testbench/dut/hart/DataStall
#add wave /testbench/dut/hart/InstrStall
#add wave /testbench/dut/hart/StallF
#add wave /testbench/dut/hart/StallD
#add wave /testbench/dut/hart/FlushD
#add wave /testbench/dut/hart/FlushE
#add wave /testbench/dut/hart/FlushM
#add wave /testbench/dut/hart/FlushW
add wave -divider Fetch
add wave -hex /testbench/dut/hart/ifu/PCF
#add wave -hex /testbench/dut/hart/ifu/icache/controller/FinalInstrRawF
add wave /testbench/InstrFName
add wave -divider Decode
add wave -hex /testbench/dut/hart/ifu/PCD
add wave -hex /testbench/dut/hart/ifu/InstrD
add wave /testbench/InstrDName
add wave -divider Execute
add wave -hex /testbench/dut/hart/ifu/PCE
add wave -hex /testbench/dut/hart/ifu/InstrE
add wave /testbench/InstrEName
add wave -divider Memory
add wave -hex /testbench/dut/hart/ifu/PCM
add wave -hex /testbench/dut/hart/ifu/InstrM
add wave /testbench/InstrMName
add wave -divider Write
add wave -hex /testbench/PCW
add wave -hex /testbench/InstrW
add wave /testbench/InstrWName
#add wave -hex /testbench/dut/hart/ieu/dp/SrcAE
#add wave -hex /testbench/dut/hart/ieu/dp/SrcBE
#add wave -hex /testbench/dut/hart/ieu/dp/ALUResultE
#add wave /testbench/dut/hart/ieu/dp/PCSrcE
add wave -divider Regfile_signals
#add wave /testbench/dut/uncore/ram/memwrite
#add wave -hex /testbench/dut/uncore/HADDR
#add wave -hex /testbench/dut/uncore/HWDATA
#add wave -divider
#add wave -hex /testbench/PCW
#add wave /testbench/InstrWName
#add wave /testbench/dut/hart/ieu/dp/RegWriteW
#add wave -hex /testbench/dut/hart/ieu/dp/ResultW
#add wave -hex /testbench/dut/hart/ieu/dp/RdW
add wave -hex -r /testbench/dut/hart/ieu/dp/regf/*
add wave -divider Regfile_itself
add wave -hex -r /testbench/dut/hart/ieu/dp/regf/rf
add wave -divider RAM
#add wave -hex -r /testbench/dut/uncore/ram/RAM
add wave -divider Misc
add wave -divider
#add wave -hex -r /testbench/*
-- Set Wave Output Items
TreeUpdate [SetDefaultTree]
WaveRestoreZoom {0 ps} {100 ps}
configure wave -namecolwidth 250
configure wave -valuecolwidth 120
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
set DefaultRadix hexadecimal
-- Run the Simulation
#run 7402000
#run 12750
run -all run -all
#run 21400 #run 21400
quit #quit

8
pipelined/regression/wave.do
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File diff suppressed because one or more lines are too long

25
pipelined/src/ifu/ifu.sv
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@ -79,7 +79,9 @@ module ifu (
// pmp/pma (inside mmu) signals. *** temporarily from AHB bus but eventually replace with internal versions pre H // pmp/pma (inside mmu) signals. *** temporarily from AHB bus but eventually replace with internal versions pre H
input var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0], input var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0],
input var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW[`PMP_ENTRIES-1:0], input var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW[`PMP_ENTRIES-1:0],
output logic InstrAccessFaultF output logic InstrAccessFaultF,
output logic ICacheAccess,
output logic ICacheMiss
); );
logic [`XLEN-1:0] PCCorrectE, UnalignedPCNextF, PCNextF; logic [`XLEN-1:0] PCCorrectE, UnalignedPCNextF, PCNextF;
@ -242,20 +244,6 @@ module ifu (
logic [1:0] IFURWF; logic [1:0] IFURWF;
assign IFURWF = CacheableF ? 2'b10 : 2'b00; assign IFURWF = CacheableF ? 2'b10 : 2'b00;
/* -----\/----- EXCLUDED -----\/-----
icache #(.LINELEN(`ICACHE_LINELENINBITS),
.NUMLINES(`ICACHE_WAYSIZEINBYTES*8/`ICACHE_LINELENINBITS),
.NUMWAYS(`ICACHE_NUMWAYS))
icache(.clk, .reset, .CPUBusy, .IgnoreRequest, .ICacheMemWriteData , .ICacheBusAck,
.ICacheBusAdr, .ICacheStallF, .FinalInstrRawF,
.ICacheFetchLine,
.IFURWF(IFURWF), //aways read
.PCNextF(PCNextFMux),
.PCPF(PCPF),
.PCF(PCFMux),
.InvalidateICacheM);
-----/\----- EXCLUDED -----/\----- */
logic [`XLEN-1:0] FinalInstrRawF_FIXME; logic [`XLEN-1:0] FinalInstrRawF_FIXME;
cache #(.LINELEN(`ICACHE_LINELENINBITS), cache #(.LINELEN(`ICACHE_LINELENINBITS),
@ -266,8 +254,8 @@ module ifu (
.CacheFetchLine(ICacheFetchLine), .CacheFetchLine(ICacheFetchLine),
.CacheWriteLine(), .CacheWriteLine(),
.ReadDataLineSets(), .ReadDataLineSets(),
.CacheMiss(), .CacheMiss(ICacheMiss),
.CacheAccess(), .CacheAccess(ICacheAccess),
.FinalWriteData('0), .FinalWriteData('0),
.RW(IFURWF), .RW(IFURWF),
.Atomic(2'b00), .Atomic(2'b00),
@ -281,9 +269,10 @@ module ifu (
end else begin end else begin
assign ICacheFetchLine = 0; assign ICacheFetchLine = 0;
assign ICacheBusAdr = 0; assign ICacheBusAdr = 0;
//assign CompressedF = 0; //?
assign ICacheStallF = 0; assign ICacheStallF = 0;
assign FinalInstrRawF = 0; assign FinalInstrRawF = 0;
assign ICacheAccess = CacheableF;
assign ICacheMiss = CacheableF;
end end
// select between dcache and direct from the BUS. Always selected if no dcache. // select between dcache and direct from the BUS. Always selected if no dcache.

2
pipelined/src/lsu/lsu.sv
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@ -318,7 +318,7 @@ module lsu
end else begin : passthrough end else begin : passthrough
assign ReadDataWordM = 0; assign ReadDataWordM = 0;
assign DCacheStall = 0; assign DCacheStall = 0;
assign DCacheMiss = 1; assign DCacheMiss = CacheableM;
assign DCacheAccess = CacheableM; assign DCacheAccess = CacheableM;
assign DCacheCommittedM = 0; assign DCacheCommittedM = 0;
assign DCacheWriteLine = 0; assign DCacheWriteLine = 0;

4
pipelined/src/privileged/csr.sv
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@ -53,6 +53,8 @@ module csr #(parameter
input logic [4:0] InstrClassM, input logic [4:0] InstrClassM,
input logic DCacheMiss, input logic DCacheMiss,
input logic DCacheAccess, input logic DCacheAccess,
input logic ICacheMiss,
input logic ICacheAccess,
input logic [1:0] NextPrivilegeModeM, PrivilegeModeW, input logic [1:0] NextPrivilegeModeM, PrivilegeModeW,
input logic [`XLEN-1:0] CauseM, NextFaultMtvalM, input logic [`XLEN-1:0] CauseM, NextFaultMtvalM,
output logic [1:0] STATUS_MPP, output logic [1:0] STATUS_MPP,
@ -131,7 +133,7 @@ module csr #(parameter
.StallE, .StallM, .StallW, .FlushE, .FlushM, .FlushW, .StallE, .StallM, .StallW, .FlushE, .FlushM, .FlushW,
.InstrValidM, .LoadStallD, .CSRMWriteM, .InstrValidM, .LoadStallD, .CSRMWriteM,
.BPPredDirWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .BPPredClassNonCFIWrongM, .BPPredDirWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .BPPredClassNonCFIWrongM,
.InstrClassM, .DCacheMiss, .DCacheAccess, .InstrClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess,
.CSRAdrM, .PrivilegeModeW, .CSRWriteValM, .CSRAdrM, .PrivilegeModeW, .CSRWriteValM,
.MCOUNTINHIBIT_REGW, .MCOUNTEREN_REGW, .SCOUNTEREN_REGW, .MCOUNTINHIBIT_REGW, .MCOUNTEREN_REGW, .SCOUNTEREN_REGW,
.MTIME_CLINT, .CSRCReadValM, .IllegalCSRCAccessM); .MTIME_CLINT, .CSRCReadValM, .IllegalCSRCAccessM);

6
pipelined/src/privileged/csrc.sv
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@ -52,6 +52,8 @@ module csrc #(parameter
input logic [4:0] InstrClassM, input logic [4:0] InstrClassM,
input logic DCacheMiss, input logic DCacheMiss,
input logic DCacheAccess, input logic DCacheAccess,
input logic ICacheMiss,
input logic ICacheAccess,
input logic [11:0] CSRAdrM, input logic [11:0] CSRAdrM,
input logic [1:0] PrivilegeModeW, input logic [1:0] PrivilegeModeW,
input logic [`XLEN-1:0] CSRWriteValM, input logic [`XLEN-1:0] CSRWriteValM,
@ -99,7 +101,9 @@ module csrc #(parameter
assign CounterEvent[10] = BPPredClassNonCFIWrongM & InstrValidNotFlushedM; assign CounterEvent[10] = BPPredClassNonCFIWrongM & InstrValidNotFlushedM;
assign CounterEvent[11] = DCacheAccess; assign CounterEvent[11] = DCacheAccess;
assign CounterEvent[12] = DCacheMiss; assign CounterEvent[12] = DCacheMiss;
assign CounterEvent[`COUNTERS-1:13] = 0; // eventually give these sources, including FP instructions, I$/D$ misses, branches and mispredictions assign CounterEvent[13] = ICacheAccess;
assign CounterEvent[14] = ICacheMiss;
assign CounterEvent[`COUNTERS-1:15] = 0; // eventually give these sources, including FP instructions, I$/D$ misses, branches and mispredictions
end end
// Counter update and write logic // Counter update and write logic

4
pipelined/src/privileged/privileged.sv
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@ -48,6 +48,8 @@ module privileged (
input logic [4:0] InstrClassM, input logic [4:0] InstrClassM,
input logic DCacheMiss, input logic DCacheMiss,
input logic DCacheAccess, input logic DCacheAccess,
input logic ICacheMiss,
input logic ICacheAccess,
input logic PrivilegedM, input logic PrivilegedM,
input logic ITLBInstrPageFaultF, DTLBLoadPageFaultM, DTLBStorePageFaultM, input logic ITLBInstrPageFaultF, DTLBLoadPageFaultM, DTLBStorePageFaultM,
input logic InstrMisalignedFaultM, IllegalIEUInstrFaultD, IllegalFPUInstrD, input logic InstrMisalignedFaultM, IllegalIEUInstrFaultD, IllegalFPUInstrD,
@ -162,7 +164,7 @@ module privileged (
.MTIME_CLINT, .MTIME_CLINT,
.InstrValidM, .FRegWriteM, .LoadStallD, .InstrValidM, .FRegWriteM, .LoadStallD,
.BPPredDirWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .BPPredDirWrongM, .BTBPredPCWrongM, .RASPredPCWrongM,
.BPPredClassNonCFIWrongM, .InstrClassM, .DCacheMiss, .DCacheAccess, .BPPredClassNonCFIWrongM, .InstrClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess,
.NextPrivilegeModeM, .PrivilegeModeW, .NextPrivilegeModeM, .PrivilegeModeW,
.CauseM, .NextFaultMtvalM, .STATUS_MPP, .CauseM, .NextFaultMtvalM, .STATUS_MPP,
.STATUS_SPP, .STATUS_TSR, .STATUS_SPP, .STATUS_TSR,

5
pipelined/src/wally/wallypipelinedhart.sv
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@ -159,6 +159,8 @@ module wallypipelinedhart (
logic PendingInterruptM; logic PendingInterruptM;
logic DCacheMiss; logic DCacheMiss;
logic DCacheAccess; logic DCacheAccess;
logic ICacheMiss;
logic ICacheAccess;
logic BreakpointFaultM, EcallFaultM; logic BreakpointFaultM, EcallFaultM;
@ -171,6 +173,7 @@ module wallypipelinedhart (
// Fetch // Fetch
.IFUBusHRDATA, .IFUBusAck, .PCF, .IFUBusAdr, .IFUBusHRDATA, .IFUBusAck, .PCF, .IFUBusAdr,
.IFUBusRead, .IFUStallF, .IFUBusRead, .IFUStallF,
.ICacheAccess, .ICacheMiss,
// Execute // Execute
.PCLinkE, .PCSrcE, .IEUAdrE, .PCE, .PCLinkE, .PCSrcE, .IEUAdrE, .PCE,
@ -322,7 +325,7 @@ module wallypipelinedhart (
.FRegWriteM, .LoadStallD, .FRegWriteM, .LoadStallD,
.BPPredDirWrongM, .BTBPredPCWrongM, .BPPredDirWrongM, .BTBPredPCWrongM,
.RASPredPCWrongM, .BPPredClassNonCFIWrongM, .RASPredPCWrongM, .BPPredClassNonCFIWrongM,
.InstrClassM, .DCacheMiss, .DCacheAccess, .PrivilegedM, .InstrClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess, .PrivilegedM,
.ITLBInstrPageFaultF, .DTLBLoadPageFaultM, .DTLBStorePageFaultM, .ITLBInstrPageFaultF, .DTLBLoadPageFaultM, .DTLBStorePageFaultM,
.InstrMisalignedFaultM, .IllegalIEUInstrFaultD, .IllegalFPUInstrD, .InstrMisalignedFaultM, .IllegalIEUInstrFaultD, .IllegalFPUInstrD,
.LoadMisalignedFaultM, .StoreMisalignedFaultM, .LoadMisalignedFaultM, .StoreMisalignedFaultM,