mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Added icache access and icache miss to performance counters.
This commit is contained in:
parent
04ea93aa27
commit
73c488914f
@ -37,82 +37,8 @@ vsim workopt
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mem load -startaddress 268435456 -endaddress 268566527 -filltype value -fillradix hex -filldata 0 /testbench/dut/uncore/ram/ram/RAM
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mem load -startaddress 268435456 -endaddress 268566527 -filltype value -fillradix hex -filldata 0 /testbench/dut/uncore/ram/ram/RAM
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view wave
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-- display input and output signals as hexidecimal values
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do wave.do
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# Diplays All Signals recursively
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add wave /testbench/clk
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add wave /testbench/reset
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add wave -divider
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#add wave /testbench/dut/hart/ebu/IReadF
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#add wave /testbench/dut/hart/DataStall
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#add wave /testbench/dut/hart/InstrStall
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#add wave /testbench/dut/hart/StallF
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#add wave /testbench/dut/hart/StallD
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#add wave /testbench/dut/hart/FlushD
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#add wave /testbench/dut/hart/FlushE
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#add wave /testbench/dut/hart/FlushM
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#add wave /testbench/dut/hart/FlushW
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add wave -divider Fetch
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add wave -hex /testbench/dut/hart/ifu/PCF
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#add wave -hex /testbench/dut/hart/ifu/icache/controller/FinalInstrRawF
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add wave /testbench/InstrFName
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add wave -divider Decode
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add wave -hex /testbench/dut/hart/ifu/PCD
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add wave -hex /testbench/dut/hart/ifu/InstrD
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add wave /testbench/InstrDName
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add wave -divider Execute
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add wave -hex /testbench/dut/hart/ifu/PCE
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add wave -hex /testbench/dut/hart/ifu/InstrE
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add wave /testbench/InstrEName
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add wave -divider Memory
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add wave -hex /testbench/dut/hart/ifu/PCM
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add wave -hex /testbench/dut/hart/ifu/InstrM
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add wave /testbench/InstrMName
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add wave -divider Write
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add wave -hex /testbench/PCW
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add wave -hex /testbench/InstrW
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add wave /testbench/InstrWName
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#add wave -hex /testbench/dut/hart/ieu/dp/SrcAE
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#add wave -hex /testbench/dut/hart/ieu/dp/SrcBE
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#add wave -hex /testbench/dut/hart/ieu/dp/ALUResultE
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#add wave /testbench/dut/hart/ieu/dp/PCSrcE
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add wave -divider Regfile_signals
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#add wave /testbench/dut/uncore/ram/memwrite
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#add wave -hex /testbench/dut/uncore/HADDR
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#add wave -hex /testbench/dut/uncore/HWDATA
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#add wave -divider
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#add wave -hex /testbench/PCW
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#add wave /testbench/InstrWName
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#add wave /testbench/dut/hart/ieu/dp/RegWriteW
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#add wave -hex /testbench/dut/hart/ieu/dp/ResultW
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#add wave -hex /testbench/dut/hart/ieu/dp/RdW
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add wave -hex -r /testbench/dut/hart/ieu/dp/regf/*
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add wave -divider Regfile_itself
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add wave -hex -r /testbench/dut/hart/ieu/dp/regf/rf
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add wave -divider RAM
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#add wave -hex -r /testbench/dut/uncore/ram/RAM
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add wave -divider Misc
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add wave -divider
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#add wave -hex -r /testbench/*
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-- Set Wave Output Items
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TreeUpdate [SetDefaultTree]
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WaveRestoreZoom {0 ps} {100 ps}
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configure wave -namecolwidth 250
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configure wave -valuecolwidth 120
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configure wave -justifyvalue left
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configure wave -signalnamewidth 0
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configure wave -snapdistance 10
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configure wave -datasetprefix 0
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configure wave -rowmargin 4
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configure wave -childrowmargin 2
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set DefaultRadix hexadecimal
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-- Run the Simulation
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#run 7402000
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#run 12750
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run -all
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run -all
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#run 21400
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#run 21400
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quit
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#quit
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File diff suppressed because one or more lines are too long
@ -79,7 +79,9 @@ module ifu (
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// pmp/pma (inside mmu) signals. *** temporarily from AHB bus but eventually replace with internal versions pre H
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// pmp/pma (inside mmu) signals. *** temporarily from AHB bus but eventually replace with internal versions pre H
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input var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0],
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input var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0],
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input var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW[`PMP_ENTRIES-1:0],
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input var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW[`PMP_ENTRIES-1:0],
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output logic InstrAccessFaultF
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output logic InstrAccessFaultF,
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output logic ICacheAccess,
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output logic ICacheMiss
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);
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);
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logic [`XLEN-1:0] PCCorrectE, UnalignedPCNextF, PCNextF;
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logic [`XLEN-1:0] PCCorrectE, UnalignedPCNextF, PCNextF;
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@ -242,20 +244,6 @@ module ifu (
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logic [1:0] IFURWF;
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logic [1:0] IFURWF;
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assign IFURWF = CacheableF ? 2'b10 : 2'b00;
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assign IFURWF = CacheableF ? 2'b10 : 2'b00;
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/* -----\/----- EXCLUDED -----\/-----
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icache #(.LINELEN(`ICACHE_LINELENINBITS),
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.NUMLINES(`ICACHE_WAYSIZEINBYTES*8/`ICACHE_LINELENINBITS),
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.NUMWAYS(`ICACHE_NUMWAYS))
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icache(.clk, .reset, .CPUBusy, .IgnoreRequest, .ICacheMemWriteData , .ICacheBusAck,
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.ICacheBusAdr, .ICacheStallF, .FinalInstrRawF,
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.ICacheFetchLine,
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.IFURWF(IFURWF), //aways read
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.PCNextF(PCNextFMux),
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.PCPF(PCPF),
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.PCF(PCFMux),
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.InvalidateICacheM);
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-----/\----- EXCLUDED -----/\----- */
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logic [`XLEN-1:0] FinalInstrRawF_FIXME;
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logic [`XLEN-1:0] FinalInstrRawF_FIXME;
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cache #(.LINELEN(`ICACHE_LINELENINBITS),
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cache #(.LINELEN(`ICACHE_LINELENINBITS),
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@ -266,8 +254,8 @@ module ifu (
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.CacheFetchLine(ICacheFetchLine),
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.CacheFetchLine(ICacheFetchLine),
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.CacheWriteLine(),
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.CacheWriteLine(),
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.ReadDataLineSets(),
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.ReadDataLineSets(),
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.CacheMiss(),
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.CacheMiss(ICacheMiss),
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.CacheAccess(),
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.CacheAccess(ICacheAccess),
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.FinalWriteData('0),
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.FinalWriteData('0),
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.RW(IFURWF),
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.RW(IFURWF),
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.Atomic(2'b00),
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.Atomic(2'b00),
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@ -281,9 +269,10 @@ module ifu (
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end else begin
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end else begin
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assign ICacheFetchLine = 0;
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assign ICacheFetchLine = 0;
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assign ICacheBusAdr = 0;
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assign ICacheBusAdr = 0;
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//assign CompressedF = 0; //?
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assign ICacheStallF = 0;
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assign ICacheStallF = 0;
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assign FinalInstrRawF = 0;
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assign FinalInstrRawF = 0;
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assign ICacheAccess = CacheableF;
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assign ICacheMiss = CacheableF;
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end
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end
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// select between dcache and direct from the BUS. Always selected if no dcache.
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// select between dcache and direct from the BUS. Always selected if no dcache.
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@ -318,7 +318,7 @@ module lsu
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end else begin : passthrough
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end else begin : passthrough
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assign ReadDataWordM = 0;
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assign ReadDataWordM = 0;
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assign DCacheStall = 0;
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assign DCacheStall = 0;
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assign DCacheMiss = 1;
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assign DCacheMiss = CacheableM;
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assign DCacheAccess = CacheableM;
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assign DCacheAccess = CacheableM;
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assign DCacheCommittedM = 0;
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assign DCacheCommittedM = 0;
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assign DCacheWriteLine = 0;
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assign DCacheWriteLine = 0;
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@ -53,6 +53,8 @@ module csr #(parameter
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input logic [4:0] InstrClassM,
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input logic [4:0] InstrClassM,
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input logic DCacheMiss,
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input logic DCacheMiss,
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input logic DCacheAccess,
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input logic DCacheAccess,
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input logic ICacheMiss,
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input logic ICacheAccess,
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input logic [1:0] NextPrivilegeModeM, PrivilegeModeW,
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input logic [1:0] NextPrivilegeModeM, PrivilegeModeW,
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input logic [`XLEN-1:0] CauseM, NextFaultMtvalM,
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input logic [`XLEN-1:0] CauseM, NextFaultMtvalM,
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output logic [1:0] STATUS_MPP,
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output logic [1:0] STATUS_MPP,
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@ -131,7 +133,7 @@ module csr #(parameter
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.StallE, .StallM, .StallW, .FlushE, .FlushM, .FlushW,
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.StallE, .StallM, .StallW, .FlushE, .FlushM, .FlushW,
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.InstrValidM, .LoadStallD, .CSRMWriteM,
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.InstrValidM, .LoadStallD, .CSRMWriteM,
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.BPPredDirWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .BPPredClassNonCFIWrongM,
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.BPPredDirWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .BPPredClassNonCFIWrongM,
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.InstrClassM, .DCacheMiss, .DCacheAccess,
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.InstrClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess,
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.CSRAdrM, .PrivilegeModeW, .CSRWriteValM,
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.CSRAdrM, .PrivilegeModeW, .CSRWriteValM,
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.MCOUNTINHIBIT_REGW, .MCOUNTEREN_REGW, .SCOUNTEREN_REGW,
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.MCOUNTINHIBIT_REGW, .MCOUNTEREN_REGW, .SCOUNTEREN_REGW,
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.MTIME_CLINT, .CSRCReadValM, .IllegalCSRCAccessM);
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.MTIME_CLINT, .CSRCReadValM, .IllegalCSRCAccessM);
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@ -52,6 +52,8 @@ module csrc #(parameter
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input logic [4:0] InstrClassM,
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input logic [4:0] InstrClassM,
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input logic DCacheMiss,
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input logic DCacheMiss,
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input logic DCacheAccess,
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input logic DCacheAccess,
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input logic ICacheMiss,
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input logic ICacheAccess,
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input logic [11:0] CSRAdrM,
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input logic [11:0] CSRAdrM,
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input logic [1:0] PrivilegeModeW,
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input logic [1:0] PrivilegeModeW,
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input logic [`XLEN-1:0] CSRWriteValM,
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input logic [`XLEN-1:0] CSRWriteValM,
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@ -99,7 +101,9 @@ module csrc #(parameter
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assign CounterEvent[10] = BPPredClassNonCFIWrongM & InstrValidNotFlushedM;
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assign CounterEvent[10] = BPPredClassNonCFIWrongM & InstrValidNotFlushedM;
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assign CounterEvent[11] = DCacheAccess;
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assign CounterEvent[11] = DCacheAccess;
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assign CounterEvent[12] = DCacheMiss;
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assign CounterEvent[12] = DCacheMiss;
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assign CounterEvent[`COUNTERS-1:13] = 0; // eventually give these sources, including FP instructions, I$/D$ misses, branches and mispredictions
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assign CounterEvent[13] = ICacheAccess;
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assign CounterEvent[14] = ICacheMiss;
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assign CounterEvent[`COUNTERS-1:15] = 0; // eventually give these sources, including FP instructions, I$/D$ misses, branches and mispredictions
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end
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end
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// Counter update and write logic
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// Counter update and write logic
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@ -48,6 +48,8 @@ module privileged (
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input logic [4:0] InstrClassM,
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input logic [4:0] InstrClassM,
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input logic DCacheMiss,
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input logic DCacheMiss,
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input logic DCacheAccess,
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input logic DCacheAccess,
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input logic ICacheMiss,
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input logic ICacheAccess,
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input logic PrivilegedM,
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input logic PrivilegedM,
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input logic ITLBInstrPageFaultF, DTLBLoadPageFaultM, DTLBStorePageFaultM,
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input logic ITLBInstrPageFaultF, DTLBLoadPageFaultM, DTLBStorePageFaultM,
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input logic InstrMisalignedFaultM, IllegalIEUInstrFaultD, IllegalFPUInstrD,
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input logic InstrMisalignedFaultM, IllegalIEUInstrFaultD, IllegalFPUInstrD,
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@ -162,7 +164,7 @@ module privileged (
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.MTIME_CLINT,
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.MTIME_CLINT,
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.InstrValidM, .FRegWriteM, .LoadStallD,
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.InstrValidM, .FRegWriteM, .LoadStallD,
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.BPPredDirWrongM, .BTBPredPCWrongM, .RASPredPCWrongM,
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.BPPredDirWrongM, .BTBPredPCWrongM, .RASPredPCWrongM,
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.BPPredClassNonCFIWrongM, .InstrClassM, .DCacheMiss, .DCacheAccess,
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.BPPredClassNonCFIWrongM, .InstrClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess,
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.NextPrivilegeModeM, .PrivilegeModeW,
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.NextPrivilegeModeM, .PrivilegeModeW,
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.CauseM, .NextFaultMtvalM, .STATUS_MPP,
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.CauseM, .NextFaultMtvalM, .STATUS_MPP,
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.STATUS_SPP, .STATUS_TSR,
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.STATUS_SPP, .STATUS_TSR,
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@ -159,6 +159,8 @@ module wallypipelinedhart (
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logic PendingInterruptM;
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logic PendingInterruptM;
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logic DCacheMiss;
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logic DCacheMiss;
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logic DCacheAccess;
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logic DCacheAccess;
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logic ICacheMiss;
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logic ICacheAccess;
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logic BreakpointFaultM, EcallFaultM;
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logic BreakpointFaultM, EcallFaultM;
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@ -171,6 +173,7 @@ module wallypipelinedhart (
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// Fetch
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// Fetch
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.IFUBusHRDATA, .IFUBusAck, .PCF, .IFUBusAdr,
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.IFUBusHRDATA, .IFUBusAck, .PCF, .IFUBusAdr,
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.IFUBusRead, .IFUStallF,
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.IFUBusRead, .IFUStallF,
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.ICacheAccess, .ICacheMiss,
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// Execute
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// Execute
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.PCLinkE, .PCSrcE, .IEUAdrE, .PCE,
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.PCLinkE, .PCSrcE, .IEUAdrE, .PCE,
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@ -322,7 +325,7 @@ module wallypipelinedhart (
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.FRegWriteM, .LoadStallD,
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.FRegWriteM, .LoadStallD,
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.BPPredDirWrongM, .BTBPredPCWrongM,
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.BPPredDirWrongM, .BTBPredPCWrongM,
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.RASPredPCWrongM, .BPPredClassNonCFIWrongM,
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.RASPredPCWrongM, .BPPredClassNonCFIWrongM,
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.InstrClassM, .DCacheMiss, .DCacheAccess, .PrivilegedM,
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.InstrClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess, .PrivilegedM,
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.ITLBInstrPageFaultF, .DTLBLoadPageFaultM, .DTLBStorePageFaultM,
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.ITLBInstrPageFaultF, .DTLBLoadPageFaultM, .DTLBStorePageFaultM,
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.InstrMisalignedFaultM, .IllegalIEUInstrFaultD, .IllegalFPUInstrD,
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.InstrMisalignedFaultM, .IllegalIEUInstrFaultD, .IllegalFPUInstrD,
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.LoadMisalignedFaultM, .StoreMisalignedFaultM,
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.LoadMisalignedFaultM, .StoreMisalignedFaultM,
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