From 73c488914f5c6f4d0032b3cf205db24e1dae79a0 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Sun, 9 Jan 2022 22:56:56 -0600 Subject: [PATCH] Added icache access and icache miss to performance counters. --- pipelined/regression/wally-coremark.do | 78 +---------------------- pipelined/regression/wave.do | 8 ++- pipelined/src/ifu/ifu.sv | 25 ++------ pipelined/src/lsu/lsu.sv | 2 +- pipelined/src/privileged/csr.sv | 4 +- pipelined/src/privileged/csrc.sv | 8 ++- pipelined/src/privileged/privileged.sv | 4 +- pipelined/src/wally/wallypipelinedhart.sv | 5 +- 8 files changed, 31 insertions(+), 103 deletions(-) diff --git a/pipelined/regression/wally-coremark.do b/pipelined/regression/wally-coremark.do index c606a4f38..e8283c583 100644 --- a/pipelined/regression/wally-coremark.do +++ b/pipelined/regression/wally-coremark.do @@ -37,82 +37,8 @@ vsim workopt mem load -startaddress 268435456 -endaddress 268566527 -filltype value -fillradix hex -filldata 0 /testbench/dut/uncore/ram/ram/RAM -view wave --- display input and output signals as hexidecimal values -# Diplays All Signals recursively -add wave /testbench/clk -add wave /testbench/reset -add wave -divider -#add wave /testbench/dut/hart/ebu/IReadF -#add wave /testbench/dut/hart/DataStall -#add wave /testbench/dut/hart/InstrStall -#add wave /testbench/dut/hart/StallF -#add wave /testbench/dut/hart/StallD -#add wave /testbench/dut/hart/FlushD -#add wave /testbench/dut/hart/FlushE -#add wave /testbench/dut/hart/FlushM -#add wave /testbench/dut/hart/FlushW - -add wave -divider Fetch -add wave -hex /testbench/dut/hart/ifu/PCF -#add wave -hex /testbench/dut/hart/ifu/icache/controller/FinalInstrRawF -add wave /testbench/InstrFName -add wave -divider Decode -add wave -hex /testbench/dut/hart/ifu/PCD -add wave -hex /testbench/dut/hart/ifu/InstrD -add wave /testbench/InstrDName -add wave -divider Execute -add wave -hex /testbench/dut/hart/ifu/PCE -add wave -hex /testbench/dut/hart/ifu/InstrE -add wave /testbench/InstrEName -add wave -divider Memory -add wave -hex /testbench/dut/hart/ifu/PCM -add wave -hex /testbench/dut/hart/ifu/InstrM -add wave /testbench/InstrMName -add wave -divider Write -add wave -hex /testbench/PCW -add wave -hex /testbench/InstrW -add wave /testbench/InstrWName -#add wave -hex /testbench/dut/hart/ieu/dp/SrcAE -#add wave -hex /testbench/dut/hart/ieu/dp/SrcBE -#add wave -hex /testbench/dut/hart/ieu/dp/ALUResultE -#add wave /testbench/dut/hart/ieu/dp/PCSrcE -add wave -divider Regfile_signals -#add wave /testbench/dut/uncore/ram/memwrite -#add wave -hex /testbench/dut/uncore/HADDR -#add wave -hex /testbench/dut/uncore/HWDATA -#add wave -divider -#add wave -hex /testbench/PCW -#add wave /testbench/InstrWName -#add wave /testbench/dut/hart/ieu/dp/RegWriteW -#add wave -hex /testbench/dut/hart/ieu/dp/ResultW -#add wave -hex /testbench/dut/hart/ieu/dp/RdW -add wave -hex -r /testbench/dut/hart/ieu/dp/regf/* -add wave -divider Regfile_itself -add wave -hex -r /testbench/dut/hart/ieu/dp/regf/rf -add wave -divider RAM -#add wave -hex -r /testbench/dut/uncore/ram/RAM -add wave -divider Misc -add wave -divider -#add wave -hex -r /testbench/* - --- Set Wave Output Items -TreeUpdate [SetDefaultTree] -WaveRestoreZoom {0 ps} {100 ps} -configure wave -namecolwidth 250 -configure wave -valuecolwidth 120 -configure wave -justifyvalue left -configure wave -signalnamewidth 0 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -set DefaultRadix hexadecimal - --- Run the Simulation -#run 7402000 -#run 12750 +do wave.do run -all #run 21400 -quit +#quit diff --git a/pipelined/regression/wave.do b/pipelined/regression/wave.do index 109a1d8b9..fa177e8c3 100644 --- a/pipelined/regression/wave.do +++ b/pipelined/regression/wave.do @@ -458,7 +458,7 @@ add wave -noupdate -group ifu -group itlb /testbench/dut/hart/ifu/ITLBMissF add wave -noupdate -group ifu -group itlb /testbench/dut/hart/ifu/immu/PhysicalAddress add wave -noupdate /testbench/dut/hart/ifu/IFUBusRead add wave -noupdate /testbench/dut/hart/ifu/icache/icache/CacheFetchLine -add wave -noupdate -radix unsigned -childformat {{{/testbench/dut/hart/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[31]} -radix unsigned} {{/testbench/dut/hart/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[30]} -radix unsigned} {{/testbench/dut/hart/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[29]} -radix unsigned} {{/testbench/dut/hart/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[28]} -radix unsigned} {{/testbench/dut/hart/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[27]} -radix unsigned} {{/testbench/dut/hart/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[26]} -radix unsigned} {{/testbench/dut/hart/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[25]} -radix unsigned} {{/testbench/dut/hart/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[24]} -radix unsigned} {{/testbench/dut/hart/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[23]} -radix unsigned} {{/testbench/dut/hart/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[22]} -radix unsigned} {{/testbench/dut/hart/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[21]} -radix unsigned} {{/testbench/dut/hart/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[20]} -radix unsigned} {{/testbench/dut/hart/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[19]} -radix unsigned} {{/testbench/dut/hart/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[18]} -radix unsigned} {{/testbench/dut/hart/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[17]} -radix unsigned} {{/testbench/dut/hart/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[16]} -radix unsigned} {{/testbench/dut/hart/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[15]} -radix unsigned} {{/testbench/dut/hart/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[14]} -radix unsigned} {{/testbench/dut/hart/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[13]} -radix unsigned} {{/testbench/dut/hart/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[12]} -radix unsigned} {{/testbench/dut/hart/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[11]} -radix unsigned} {{/testbench/dut/hart/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[10]} -radix unsigned} {{/testbench/dut/hart/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[9]} -radix unsigned} {{/testbench/dut/hart/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[8]} -radix unsigned} {{/testbench/dut/hart/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[7]} -radix unsigned} {{/testbench/dut/hart/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[6]} -radix unsigned} {{/testbench/dut/hart/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[5]} -radix unsigned} {{/testbench/dut/hart/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[4]} -radix unsigned} {{/testbench/dut/hart/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[3]} -radix unsigned} {{/testbench/dut/hart/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[2]} -radix unsigned} {{/testbench/dut/hart/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[1]} -radix unsigned} {{/testbench/dut/hart/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[0]} -radix unsigned}} -subitemconfig {{/testbench/dut/hart/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[31]} {-radix unsigned} {/testbench/dut/hart/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[30]} {-radix unsigned} {/testbench/dut/hart/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[29]} {-radix unsigned} {/testbench/dut/hart/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[28]} {-radix unsigned} {/testbench/dut/hart/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[27]} {-radix unsigned} {/testbench/dut/hart/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[26]} {-radix unsigned} {/testbench/dut/hart/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[25]} {-radix unsigned} {/testbench/dut/hart/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[24]} {-radix unsigned} {/testbench/dut/hart/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[23]} {-radix unsigned} {/testbench/dut/hart/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[22]} {-radix unsigned} {/testbench/dut/hart/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[21]} {-radix unsigned} {/testbench/dut/hart/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[20]} {-radix unsigned} {/testbench/dut/hart/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[19]} {-radix unsigned} {/testbench/dut/hart/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[18]} {-radix unsigned} {/testbench/dut/hart/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[17]} {-radix unsigned} {/testbench/dut/hart/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[16]} {-radix unsigned} {/testbench/dut/hart/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[15]} {-radix unsigned} {/testbench/dut/hart/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[14]} {-radix unsigned} {/testbench/dut/hart/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[13]} {-radix unsigned} {/testbench/dut/hart/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[12]} {-radix unsigned} {/testbench/dut/hart/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[11]} {-radix unsigned} {/testbench/dut/hart/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[10]} {-radix unsigned} {/testbench/dut/hart/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[9]} {-radix unsigned} {/testbench/dut/hart/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[8]} {-radix unsigned} {/testbench/dut/hart/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[7]} {-radix unsigned} {/testbench/dut/hart/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[6]} {-radix unsigned} {/testbench/dut/hart/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[5]} {-radix unsigned} {/testbench/dut/hart/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[4]} {-radix unsigned} {/testbench/dut/hart/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[3]} {-radix unsigned} {/testbench/dut/hart/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[2]} {-radix unsigned} {/testbench/dut/hart/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[1]} {-radix unsigned} {/testbench/dut/hart/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[0]} {-radix unsigned}} /testbench/dut/hart/priv/priv/csr/counters/counters/HPMCOUNTER_REGW +add wave -noupdate -radix unsigned -childformat {{{/testbench/dut/hart/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[31]} -radix unsigned} {{/testbench/dut/hart/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[30]} -radix unsigned} {{/testbench/dut/hart/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[29]} -radix unsigned} {{/testbench/dut/hart/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[28]} -radix unsigned} {{/testbench/dut/hart/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[27]} -radix unsigned} {{/testbench/dut/hart/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[26]} -radix unsigned} {{/testbench/dut/hart/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[25]} -radix unsigned} {{/testbench/dut/hart/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[24]} -radix unsigned} {{/testbench/dut/hart/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[23]} -radix unsigned} {{/testbench/dut/hart/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[22]} -radix unsigned} {{/testbench/dut/hart/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[21]} -radix unsigned} {{/testbench/dut/hart/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[20]} -radix unsigned} {{/testbench/dut/hart/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[19]} -radix unsigned} {{/testbench/dut/hart/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[18]} -radix unsigned} {{/testbench/dut/hart/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[17]} -radix unsigned} {{/testbench/dut/hart/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[16]} -radix unsigned} {{/testbench/dut/hart/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[15]} -radix unsigned} {{/testbench/dut/hart/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[14]} -radix unsigned} {{/testbench/dut/hart/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[13]} -radix unsigned} {{/testbench/dut/hart/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[12]} -radix unsigned} {{/testbench/dut/hart/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[11]} -radix unsigned} {{/testbench/dut/hart/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[10]} -radix unsigned} {{/testbench/dut/hart/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[9]} -radix unsigned} {{/testbench/dut/hart/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[8]} -radix unsigned} {{/testbench/dut/hart/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[7]} -radix unsigned} {{/testbench/dut/hart/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[6]} -radix unsigned} {{/testbench/dut/hart/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[5]} -radix unsigned} {{/testbench/dut/hart/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[4]} -radix unsigned} {{/testbench/dut/hart/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[3]} -radix unsigned} {{/testbench/dut/hart/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[2]} -radix unsigned} {{/testbench/dut/hart/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[1]} -radix unsigned} {{/testbench/dut/hart/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[0]} -radix unsigned}} -subitemconfig {{/testbench/dut/hart/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[31]} {-height 16 -radix unsigned} {/testbench/dut/hart/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[30]} {-height 16 -radix unsigned} {/testbench/dut/hart/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[29]} {-height 16 -radix unsigned} {/testbench/dut/hart/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[28]} {-height 16 -radix unsigned} {/testbench/dut/hart/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[27]} {-height 16 -radix unsigned} {/testbench/dut/hart/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[26]} {-height 16 -radix unsigned} {/testbench/dut/hart/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[25]} {-height 16 -radix unsigned} {/testbench/dut/hart/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[24]} {-height 16 -radix unsigned} {/testbench/dut/hart/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[23]} {-height 16 -radix unsigned} {/testbench/dut/hart/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[22]} {-height 16 -radix unsigned} {/testbench/dut/hart/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[21]} {-height 16 -radix unsigned} {/testbench/dut/hart/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[20]} {-height 16 -radix unsigned} {/testbench/dut/hart/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[19]} {-height 16 -radix unsigned} {/testbench/dut/hart/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[18]} {-height 16 -radix unsigned} {/testbench/dut/hart/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[17]} {-height 16 -radix unsigned} {/testbench/dut/hart/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[16]} {-height 16 -radix unsigned} {/testbench/dut/hart/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[15]} {-height 16 -radix unsigned} {/testbench/dut/hart/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[14]} {-height 16 -radix unsigned} {/testbench/dut/hart/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[13]} {-height 16 -radix unsigned} {/testbench/dut/hart/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[12]} {-height 16 -radix unsigned} {/testbench/dut/hart/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[11]} {-height 16 -radix unsigned} {/testbench/dut/hart/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[10]} {-height 16 -radix unsigned} {/testbench/dut/hart/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[9]} {-height 16 -radix unsigned} {/testbench/dut/hart/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[8]} {-height 16 -radix unsigned} {/testbench/dut/hart/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[7]} {-height 16 -radix unsigned} {/testbench/dut/hart/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[6]} {-height 16 -radix unsigned} {/testbench/dut/hart/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[5]} {-height 16 -radix unsigned} {/testbench/dut/hart/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[4]} {-height 16 -radix unsigned} {/testbench/dut/hart/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[3]} {-height 16 -radix unsigned} {/testbench/dut/hart/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[2]} {-height 16 -radix unsigned} {/testbench/dut/hart/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[1]} {-height 16 -radix unsigned} {/testbench/dut/hart/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[0]} {-height 16 -radix unsigned}} /testbench/dut/hart/priv/priv/csr/counters/counters/HPMCOUNTER_REGW add wave -noupdate -expand -group {Performance Counters} -label MCYCLE -radix unsigned {/testbench/dut/hart/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[0]} add wave -noupdate -expand -group {Performance Counters} -label MINSTRET -radix unsigned {/testbench/dut/hart/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[2]} add wave -noupdate -expand -group {Performance Counters} -label {LOAD STORE HAZARD} -radix unsigned {/testbench/dut/hart/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[3]} @@ -469,10 +469,12 @@ add wave -noupdate -expand -group {Performance Counters} -expand -group BRP -lab add wave -noupdate -expand -group {Performance Counters} -expand -group BRP -label {RAS WRONG} -radix unsigned {/testbench/dut/hart/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[8]} add wave -noupdate -expand -group {Performance Counters} -expand -group BRP -label {RETURN INSTRUCTION} -radix unsigned {/testbench/dut/hart/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[9]} add wave -noupdate -expand -group {Performance Counters} -expand -group BRP -label {BP CLASS WRONG} -radix unsigned {/testbench/dut/hart/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[10]} +add wave -noupdate -expand -group {Performance Counters} -expand -group ICACHE -label {ICACHE ACCESS} -radix unsigned {/testbench/dut/hart/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[13]} +add wave -noupdate -expand -group {Performance Counters} -expand -group ICACHE -label {ICACHE MISS} -radix unsigned {/testbench/dut/hart/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[14]} add wave -noupdate -expand -group {Performance Counters} -expand -group DCACHE -label {DCACHE ACCESS} -radix unsigned {/testbench/dut/hart/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[11]} add wave -noupdate -expand -group {Performance Counters} -expand -group DCACHE -label {DCACHE MISS} -radix unsigned {/testbench/dut/hart/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[12]} TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 7} {41126201 ns} 0} {{Cursor 5} {49445 ns} 1} {{Cursor 3} {235459 ns} 1} {{Cursor 4} {217231 ns} 1} +WaveRestoreCursors {{Cursor 7} {58343 ns} 0} {{Cursor 5} {49445 ns} 1} {{Cursor 3} {235459 ns} 1} {{Cursor 4} {217231 ns} 1} quietly wave cursor active 1 configure wave -namecolwidth 250 configure wave -valuecolwidth 314 @@ -488,4 +490,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {0 ns} {90866312 ns} +WaveRestoreZoom {0 ns} {244629 ns} diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv index e4307b4ed..2dd67bf1f 100644 --- a/pipelined/src/ifu/ifu.sv +++ b/pipelined/src/ifu/ifu.sv @@ -79,7 +79,9 @@ module ifu ( // pmp/pma (inside mmu) signals. *** temporarily from AHB bus but eventually replace with internal versions pre H input var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0], input var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW[`PMP_ENTRIES-1:0], - output logic InstrAccessFaultF + output logic InstrAccessFaultF, + output logic ICacheAccess, + output logic ICacheMiss ); logic [`XLEN-1:0] PCCorrectE, UnalignedPCNextF, PCNextF; @@ -242,20 +244,6 @@ module ifu ( logic [1:0] IFURWF; assign IFURWF = CacheableF ? 2'b10 : 2'b00; -/* -----\/----- EXCLUDED -----\/----- - icache #(.LINELEN(`ICACHE_LINELENINBITS), - .NUMLINES(`ICACHE_WAYSIZEINBYTES*8/`ICACHE_LINELENINBITS), - .NUMWAYS(`ICACHE_NUMWAYS)) - icache(.clk, .reset, .CPUBusy, .IgnoreRequest, .ICacheMemWriteData , .ICacheBusAck, - .ICacheBusAdr, .ICacheStallF, .FinalInstrRawF, - .ICacheFetchLine, - .IFURWF(IFURWF), //aways read - .PCNextF(PCNextFMux), - .PCPF(PCPF), - .PCF(PCFMux), - .InvalidateICacheM); - -----/\----- EXCLUDED -----/\----- */ - logic [`XLEN-1:0] FinalInstrRawF_FIXME; cache #(.LINELEN(`ICACHE_LINELENINBITS), @@ -266,8 +254,8 @@ module ifu ( .CacheFetchLine(ICacheFetchLine), .CacheWriteLine(), .ReadDataLineSets(), - .CacheMiss(), - .CacheAccess(), + .CacheMiss(ICacheMiss), + .CacheAccess(ICacheAccess), .FinalWriteData('0), .RW(IFURWF), .Atomic(2'b00), @@ -281,9 +269,10 @@ module ifu ( end else begin assign ICacheFetchLine = 0; assign ICacheBusAdr = 0; - //assign CompressedF = 0; //? assign ICacheStallF = 0; assign FinalInstrRawF = 0; + assign ICacheAccess = CacheableF; + assign ICacheMiss = CacheableF; end // select between dcache and direct from the BUS. Always selected if no dcache. diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv index 44c0b3464..d716377f4 100644 --- a/pipelined/src/lsu/lsu.sv +++ b/pipelined/src/lsu/lsu.sv @@ -318,7 +318,7 @@ module lsu end else begin : passthrough assign ReadDataWordM = 0; assign DCacheStall = 0; - assign DCacheMiss = 1; + assign DCacheMiss = CacheableM; assign DCacheAccess = CacheableM; assign DCacheCommittedM = 0; assign DCacheWriteLine = 0; diff --git a/pipelined/src/privileged/csr.sv b/pipelined/src/privileged/csr.sv index 9f7860099..76dd0f272 100644 --- a/pipelined/src/privileged/csr.sv +++ b/pipelined/src/privileged/csr.sv @@ -53,6 +53,8 @@ module csr #(parameter input logic [4:0] InstrClassM, input logic DCacheMiss, input logic DCacheAccess, + input logic ICacheMiss, + input logic ICacheAccess, input logic [1:0] NextPrivilegeModeM, PrivilegeModeW, input logic [`XLEN-1:0] CauseM, NextFaultMtvalM, output logic [1:0] STATUS_MPP, @@ -131,7 +133,7 @@ module csr #(parameter .StallE, .StallM, .StallW, .FlushE, .FlushM, .FlushW, .InstrValidM, .LoadStallD, .CSRMWriteM, .BPPredDirWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .BPPredClassNonCFIWrongM, - .InstrClassM, .DCacheMiss, .DCacheAccess, + .InstrClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess, .CSRAdrM, .PrivilegeModeW, .CSRWriteValM, .MCOUNTINHIBIT_REGW, .MCOUNTEREN_REGW, .SCOUNTEREN_REGW, .MTIME_CLINT, .CSRCReadValM, .IllegalCSRCAccessM); diff --git a/pipelined/src/privileged/csrc.sv b/pipelined/src/privileged/csrc.sv index d04c17140..7fde50036 100644 --- a/pipelined/src/privileged/csrc.sv +++ b/pipelined/src/privileged/csrc.sv @@ -52,6 +52,8 @@ module csrc #(parameter input logic [4:0] InstrClassM, input logic DCacheMiss, input logic DCacheAccess, + input logic ICacheMiss, + input logic ICacheAccess, input logic [11:0] CSRAdrM, input logic [1:0] PrivilegeModeW, input logic [`XLEN-1:0] CSRWriteValM, @@ -98,8 +100,10 @@ module csrc #(parameter assign CounterEvent[9] = InstrClassM[3] & InstrValidNotFlushedM; assign CounterEvent[10] = BPPredClassNonCFIWrongM & InstrValidNotFlushedM; assign CounterEvent[11] = DCacheAccess; - assign CounterEvent[12] = DCacheMiss; - assign CounterEvent[`COUNTERS-1:13] = 0; // eventually give these sources, including FP instructions, I$/D$ misses, branches and mispredictions + assign CounterEvent[12] = DCacheMiss; + assign CounterEvent[13] = ICacheAccess; + assign CounterEvent[14] = ICacheMiss; + assign CounterEvent[`COUNTERS-1:15] = 0; // eventually give these sources, including FP instructions, I$/D$ misses, branches and mispredictions end // Counter update and write logic diff --git a/pipelined/src/privileged/privileged.sv b/pipelined/src/privileged/privileged.sv index 6adaa2490..0c0e3184a 100644 --- a/pipelined/src/privileged/privileged.sv +++ b/pipelined/src/privileged/privileged.sv @@ -48,6 +48,8 @@ module privileged ( input logic [4:0] InstrClassM, input logic DCacheMiss, input logic DCacheAccess, + input logic ICacheMiss, + input logic ICacheAccess, input logic PrivilegedM, input logic ITLBInstrPageFaultF, DTLBLoadPageFaultM, DTLBStorePageFaultM, input logic InstrMisalignedFaultM, IllegalIEUInstrFaultD, IllegalFPUInstrD, @@ -162,7 +164,7 @@ module privileged ( .MTIME_CLINT, .InstrValidM, .FRegWriteM, .LoadStallD, .BPPredDirWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, - .BPPredClassNonCFIWrongM, .InstrClassM, .DCacheMiss, .DCacheAccess, + .BPPredClassNonCFIWrongM, .InstrClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess, .NextPrivilegeModeM, .PrivilegeModeW, .CauseM, .NextFaultMtvalM, .STATUS_MPP, .STATUS_SPP, .STATUS_TSR, diff --git a/pipelined/src/wally/wallypipelinedhart.sv b/pipelined/src/wally/wallypipelinedhart.sv index 7487a5085..6d798b3f2 100644 --- a/pipelined/src/wally/wallypipelinedhart.sv +++ b/pipelined/src/wally/wallypipelinedhart.sv @@ -159,6 +159,8 @@ module wallypipelinedhart ( logic PendingInterruptM; logic DCacheMiss; logic DCacheAccess; + logic ICacheMiss; + logic ICacheAccess; logic BreakpointFaultM, EcallFaultM; @@ -171,6 +173,7 @@ module wallypipelinedhart ( // Fetch .IFUBusHRDATA, .IFUBusAck, .PCF, .IFUBusAdr, .IFUBusRead, .IFUStallF, + .ICacheAccess, .ICacheMiss, // Execute .PCLinkE, .PCSrcE, .IEUAdrE, .PCE, @@ -322,7 +325,7 @@ module wallypipelinedhart ( .FRegWriteM, .LoadStallD, .BPPredDirWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .BPPredClassNonCFIWrongM, - .InstrClassM, .DCacheMiss, .DCacheAccess, .PrivilegedM, + .InstrClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess, .PrivilegedM, .ITLBInstrPageFaultF, .DTLBLoadPageFaultM, .DTLBStorePageFaultM, .InstrMisalignedFaultM, .IllegalIEUInstrFaultD, .IllegalFPUInstrD, .LoadMisalignedFaultM, .StoreMisalignedFaultM,