Merge pull request #491 from ross144/main

Running ImperasDV Linux is upto date

config/buildroot/config.vh

@@ -45,7 +45,7 @@ localparam SSTC_SUPPORTED = 1;
 localparam ZICBOM_SUPPORTED = 1;
 localparam ZICBOZ_SUPPORTED = 1;
 localparam ZICBOP_SUPPORTED = 1;
-localparam ZICCLSM_SUPPORTED = 0;
+localparam ZICCLSM_SUPPORTED = 1;
 localparam SVPBMT_SUPPORTED = 1;
 localparam SVNAPOT_SUPPORTED = 1;
 localparam SVINVAL_SUPPORTED = 1;

fpga/constraints/marked_debug.txt

@@ -1,132 +1,12 @@
-lsu/lsu.sv: logic      IEUAdrM
-lsu/lsu.sv: logic      WriteDataM
-lsu/lsu.sv: logic        LSUHADDR
-lsu/lsu.sv: logic        HRDATA
-lsu/lsu.sv: logic        LSUHWDATA
-lsu/lsu.sv: logic       LSUHREADY
-lsu/lsu.sv: logic       LSUHWRITE
-lsu/lsu.sv: logic        LSUHSIZE
-lsu/lsu.sv: logic        LSUHBURST
-lsu/lsu.sv: logic        LSUHTRANS
-lsu/lsu.sv: logic        LSUHWSTRB
-lsu/lsu.sv: logic      IHAdrM
-ieu/regfile.sv: logic    rf
-ieu/datapath.sv: logic                 RegWriteW
-hazard/hazard.sv: logic	         BPPredWrongE
-hazard/hazard.sv: logic	         LoadStallD
-hazard/hazard.sv: logic          FCvtIntStallD
-hazard/hazard.sv: logic	         DivBusyE
-hazard/hazard.sv: logic	         EcallFaultM
-hazard/hazard.sv: logic          WFIStallM
-hazard/hazard.sv: logic	        StallF
-hazard/hazard.sv: logic	        FlushD
-cache/cachefsm.sv:   statetype CurrState
-wally/wallypipelinedcore.sv: logic    TrapM
-wally/wallypipelinedcore.sv: logic            SrcAM
-wally/wallypipelinedcore.sv: logic                 InstrM
 wally/wallypipelinedcore.sv: logic             PCM
-wally/wallypipelinedcore.sv: logic           MemRWM
+wally/wallypipelinedcore.sv: logic    TrapM
 wally/wallypipelinedcore.sv: logic                InstrValidM
-wally/wallypipelinedcore.sv: logic     WriteDataM
+wally/wallypipelinedcore.sv: logic                 InstrM
-wally/wallypipelinedcore.sv: logic     IEUAdrM
+lsu/lsu.sv: logic        IEUAdrM
-wally/wallypipelinedcore.sv: logic   HRDATA
+lsu/lsu.sv: logic        PAdrM
-ifu/spill.sv:    statetype CurrState
+lsu/lsu.sv: logic        ReadDataM
-ifu/ifu.sv: logic    				IFUStallF
+lsu/lsu.sv: logic        WriteDataM
-ifu/ifu.sv: logic     IFUHADDR
+lsu/lsu.sv: logic       MemRWM
-ifu/ifu.sv: logic     	HRDATA
+mmu/hptw.sv: logic	   SATP_REGW
-ifu/ifu.sv: logic      IFUHREADY
+privileged/csr.sv: logic       MENVCFG_REGW
-ifu/ifu.sv: logic     IFUHWRITE
+privileged/csr.sv: logic       SENVCFG_REGW
-ifu/ifu.sv: logic      IFUHSIZE
-ifu/ifu.sv: logic      IFUHBURST
-ifu/ifu.sv: logic      IFUHTRANS
-ifu/ifu.sv: logic     PCF
-ifu/ifu.sv: logic                 PCNextF
-ifu/ifu.sv: logic            PCPF
-ifu/ifu.sv: logic     PostSpillInstrRawF
-mmu/hptw.sv: logic	   ITLBWriteF
-mmu/hptw.sv:	 statetype WalkerState
-mmu/hptw.sv: logic ValidPTE
-privileged/csrs.sv: logic        CSRSReadValM
-privileged/csrs.sv: logic        SEPC_REGW
-privileged/csrs.sv: logic        MIP_REGW
-privileged/csrs.sv: logic      SSCRATCH_REGW
-privileged/csrs.sv: logic     SCAUSE_REGW      
-privileged/csr.sv: logic    CSRReadValM  
-privileged/csr.sv: logic    CSRSrcM
-privileged/csr.sv: logic    CSRWriteValM
-privileged/csr.sv: logic    MSTATUS_REGW
-privileged/trap.sv: logic      		   InstrMisalignedFaultM
-privileged/trap.sv: logic      		   BreakpointFaultM
-privileged/trap.sv: logic      		   LoadAccessFaultM
-privileged/trap.sv: logic      		   LoadPageFaultM
-privileged/trap.sv: logic      		   mretM
-privileged/trap.sv: logic      MIP_REGW
-privileged/trap.sv: logic           PendingIntsM
-privileged/privileged.sv: logic      CSRReadM
-privileged/privileged.sv: logic    InterruptM
-privileged/csrc.sv: logic      HPMCOUNTER_REGW
-privileged/csri.sv: logic       MExtInt
-privileged/csri.sv: logic        MIP_REGW_writeabl
-privileged/csrm.sv: logic        	     MIP_REGW
-privileged/csrm.sv: logic       MEPC_REGW
-privileged/csrm.sv: logic     MEDELEG_REGW
-privileged/csrm.sv: logic          MIDELEG_REGW
-privileged/csrm.sv: logic      MSCRATCH_REGW
-privileged/csrm.sv: logic       MCAUSE_REGW
-uncore/uart_apb.sv: logic                  SIN
-uncore/uart_apb.sv: logic                 SOUT
-uncore/uart_apb.sv: logic                 OUT1b
-uncore/uartPC16550D.sv: logic       RBR
-uncore/uartPC16550D.sv: logic        FCR
-uncore/uartPC16550D.sv: logic        IER
-uncore/uartPC16550D.sv: logic        MCR
-uncore/uartPC16550D.sv: logic    	   baudpulse
-uncore/uartPC16550D.sv:     statetype rxstate
-uncore/uartPC16550D.sv: logic     					rxfifo
-uncore/uartPC16550D.sv: logic     					txfifo
-uncore/uartPC16550D.sv: logic    					rxfifohead
-uncore/uartPC16550D.sv: logic    					rxfifoentries
-uncore/uartPC16550D.sv: logic       					RXBR
-uncore/uartPC16550D.sv: logic     					rxtimeoutcnt
-uncore/uartPC16550D.sv: logic      						rxparityerr
-uncore/uartPC16550D.sv: logic   						rxdataready
-uncore/uartPC16550D.sv: logic   						rxfifoempty
-uncore/uartPC16550D.sv: logic     					rxdata
-uncore/uartPC16550D.sv: logic     					RXerrbit
-uncore/uartPC16550D.sv: logic     					rxfullbitunwrapped
-uncore/uartPC16550D.sv: logic     					txdata
-uncore/uartPC16550D.sv: logic    						txnextbit
-uncore/uartPC16550D.sv: logic    						txfifoempty
-uncore/uartPC16550D.sv: logic   						fifoenabled
-uncore/uartPC16550D.sv: logic   						RXerr
-uncore/uartPC16550D.sv: logic   						THRE
-uncore/uartPC16550D.sv: logic   						rxdataavailintr
-uncore/uartPC16550D.sv: logic    					intrID
-uncore/uncore.sv: logic HSELEXTSDCD
-uncore/plic_apb.sv: logic                    MExtInt
-uncore/plic_apb.sv: logic     Din
-uncore/plic_apb.sv: logic             requests
-uncore/plic_apb.sv: logic        intPriority
-uncore/plic_apb.sv: logic             intInProgress
-uncore/plic_apb.sv: logic           intThreshold
-uncore/plic_apb.sv: logic             intEn
-uncore/plic_apb.sv: logic           intClaim
-uncore/plic_apb.sv: logic        irqMatrix
-uncore/plic_apb.sv: logic           priorities_with_irqs
-uncore/plic_apb.sv: logic           max_priority_with_irqs
-uncore/plic_apb.sv: logic          irqs_at_max_priority
-uncore/plic_apb.sv: logic           threshMask
-uncore/clint_apb.sv: logic      MTIME
-uncore/clint_apb.sv: logic         MTIMECMP
-ebu/ebu.sv: logic     HCLK
-ebu/ebu.sv: logic      HREADY
-ebu/ebu.sv: logic      HRESP
-ebu/ebu.sv: logic      HADDR
-ebu/ebu.sv: logic     HWRITE
-ebu/ebu.sv: logic      HSIZE
-ebu/ebu.sv: logic      HBURST
-ebu/ebu.sv: logic      HPROT
-ebu/ebu.sv: logic      HTRANS
-ebu/ebu.sv: logic     HMASTLOC
-ebu/buscachefsm.sv:   busstatetype CurrState
-ebu/busfsm.sv:   busstatetype CurrState

linux/devicetree/wally-vcu118.dts

@@ -31,6 +31,7 @@
 			status = "okay";
 			compatible = "riscv";
 			riscv,isa = "rv64imafdcsu";
+                        riscv,isa-extensions = "imafdc", "sstc", "svinval", "svnapot", "svpbmt", "zba", "zbb", "zbc", "zbs", "zicbom", "zicbop", "zicbopz", "zicntr", "zicsr", "zifencei", "zihpm";
 			mmu-type = "riscv,sv48";
 
 			interrupt-controller {

sim/imperas.ic

@@ -91,7 +91,7 @@
 
 # Add Imperas simulator application instruction tracing
 --verbose
---trace --tracechange --traceshowicount --tracemode -tracemem ASX --monitornetschange --traceafter 0
+#--trace --tracechange --traceshowicount --tracemode -tracemem ASX --monitornetschange --traceafter 300000000
 --override cpu/debugflags=6 --override cpu/verbose=1
 --override cpu/show_c_prefix=T
 

sim/run-imperas-linux.sh

@@ -7,4 +7,4 @@ export OTHERFLAGS="+TRACE2LOG_ENABLE=1"
 #export OTHERFLAGS="+TRACE2LOG_ENABLE=1  +TRACE2LOG_AFTER=10500000"
 export OTHERFLAGS=""
 
-vsim -c -do "do wally-linux-imperas.do buildroot buildroot-no-trace $::env(RISCV) 0 0 0"
+vsim -c  -do "do wally-linux-imperas.do buildroot buildroot-no-trace $::env(RISCV) 0 0 0"

sim/wally-linux-imperas.do

@@ -40,6 +40,7 @@ if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} {
 
     #-- Run the Simulation
     #run -all
+    run 7000 ms
     add log -recursive /*
     do linux-wave.do
     run -all
@@ -87,9 +88,10 @@ if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} {
     #run 100 ns
     #force -deposit testbench/dut/core/priv/priv/csr/csri/IE_REGW 16'h2aa
     #force -deposit testbench/dut/uncore/uncore/clint/clint/MTIMECMP 64'h1000
+    run 7000 ms
+    add log -recursive /testbench/dut/*
+    do wave.do
     run 14000 ms
-    #add log -recursive /*
-    #do linux-wave.do
     #run -all
 
     exec ./slack-notifier/slack-notifier.py

src/cache/cache.sv

@@ -98,6 +98,7 @@ module cache import cvw::*; #(parameter cvw_t P,
   logic [LINELEN-1:0]            ReadDataLine, ReadDataLineCache;
   logic                          SelFetchBuffer;
   logic                          CacheEn;
+  logic                          SelWay;
   logic [LINELEN/8-1:0]          LineByteMask;
   logic [$clog2(LINELEN/8) - $clog2(MUXINTERVAL/8) - 1:0] WordOffsetAddr;
   logic                                                   ZeroCacheLine;
@@ -119,7 +120,7 @@ module cache import cvw::*; #(parameter cvw_t P,
 
   // Array of cache ways, along with victim, hit, dirty, and read merging logic
   cacheway #(P, PA_BITS, XLEN, NUMLINES, LINELEN, TAGLEN, OFFSETLEN, SETLEN, READ_ONLY_CACHE) CacheWays[NUMWAYS-1:0](
-    .clk, .reset, .CacheEn, .CMOp, .CacheSet, .PAdr, .LineWriteData, .LineByteMask,
+    .clk, .reset, .CacheEn, .CMOp, .CacheSet, .PAdr, .LineWriteData, .LineByteMask, .SelWay,
     .SetValid, .ClearValid, .SetDirty, .ClearDirty, .CMOZeroHit, .SelWriteback, .SelCMOWriteback, .VictimWay,
     .FlushWay, .SelFlush, .ReadDataLineWay, .HitWay, .ValidWay, .DirtyWay, .TagWay, .FlushStage, .InvalidateCache);
 
@@ -231,7 +232,7 @@ module cache import cvw::*; #(parameter cvw_t P,
   cachefsm #(P, READ_ONLY_CACHE) cachefsm(.clk, .reset, .CacheBusRW, .CacheBusAck, 
     .FlushStage, .CacheRW, .CacheAtomic, .Stall,
     .CacheHit, .LineDirty, .CacheStall, .CacheCommitted, 
-    .CacheMiss, .CacheAccess, .SelAdr, 
+    .CacheMiss, .CacheAccess, .SelAdr, .SelWay,
     .ClearDirty, .SetDirty, .SetValid, .ClearValid, .ZeroCacheLine, .CMOZeroHit, .SelWriteback, .SelCMOWriteback, .SelFlush,
     .FlushAdrCntEn, .FlushWayCntEn, .FlushCntRst,
     .FlushAdrFlag, .FlushWayFlag, .FlushCache, .SelFetchBuffer,

src/cache/cachefsm.sv

@@ -65,6 +65,7 @@ module cachefsm import cvw::*; #(parameter cvw_t P,
   output logic       SelCMOWriteback,   // Overrides cached tag check to select a specific way and set for writeback for both data and tag
   output logic       LRUWriteEn,        // Update the LRU state
   output logic       SelFlush,          // [0] Use SelAdr, [1] SRAM reads/writes from FlushAdr
+  output logic       SelWay,            // Controls which way to select a way data and tag, 00 = hitway, 10 = victimway, 11 = flushway
   output logic       FlushAdrCntEn,     // Enable the counter for Flush Adr
   output logic       FlushWayCntEn,     // Enable the way counter during a flush
   output logic       FlushCntRst,       // Reset both flush counters
@@ -166,7 +167,7 @@ module cachefsm import cvw::*; #(parameter cvw_t P,
   // write enables internal to cache
   assign CMOZeroHit = CurrState == STATE_READY & CMOp[3] & CacheHit ;
   assign SetValid = CurrState == STATE_WRITE_LINE | 
-                    (CurrState == STATE_READY & CMOZeroNoEviction) |
+                    (P.ZICBOZ_SUPPORTED & CurrState == STATE_READY & CMOZeroNoEviction) |
                     (P.ZICBOZ_SUPPORTED & CurrState == STATE_WRITEBACK & CacheBusAck & CMOp[3]); 
   assign ClearValid = P.ZICBOM_SUPPORTED & ((CurrState == STATE_READY & CMOp[0] & CacheHit) |
                       (CurrState == STATE_CMO_WRITEBACK & CMOp[2] & CacheBusAck));
@@ -182,6 +183,11 @@ module cachefsm import cvw::*; #(parameter cvw_t P,
                       (CurrState == STATE_FLUSH & LineDirty) | // This is wrong in a multicore snoop cache protocal.  Dirty must be cleared concurrently and atomically with writeback.  For single core cannot clear after writeback on bus ack and change flushadr.  Clears the wrong set.
   // Flush and eviction controls
                       (P.ZICBOM_SUPPORTED & CurrState == STATE_CMO_WRITEBACK & (CMOp[1] | CMOp[2]) & CacheBusAck);
+  assign SelWay = SelWriteback | (CurrState == STATE_WRITE_LINE) |
+                  // This is almost the same as setvalid, but on cachehit we don't want to select
+                  // the nonhit way, but instead want to force this to zero
+                  (P.ZICBOZ_SUPPORTED & CurrState == STATE_READY & CMOZeroNoEviction & ~CacheHit) |
+                  (P.ZICBOZ_SUPPORTED & CurrState == STATE_WRITEBACK & CacheBusAck & CMOp[3]);
   assign ZeroCacheLine = P.ZICBOZ_SUPPORTED & ((CurrState == STATE_READY & CMOZeroNoEviction) | 
                                                (CurrState == STATE_WRITEBACK & (CMOp[3] & CacheBusAck)));  
   assign SelWriteback = (CurrState == STATE_WRITEBACK & ~CacheBusAck) |

src/cache/cacheway.sv

@@ -41,7 +41,8 @@ module cacheway import cvw::*; #(parameter cvw_t P,
   input  logic                        SetValid,       // Set the valid bit in the selected way and set
   input  logic                        ClearValid,     // Clear the valid bit in the selected way and set
   input  logic                        SetDirty,       // Set the dirty bit in the selected way and set
-  input  logic                        CMOZeroHit,  // Write zeros to all bytes of a cache line
+  input  logic                        SelWay,         // Controls which way to select a way data and tag, 00 = hitway, 10 = victimway, 11 = flushway
+  input  logic                        CMOZeroHit,     // Write zeros to all bytes of a cache line
   input  logic                        ClearDirty,     // Clear the dirty bit in the selected way and set
   input  logic                        SelWriteback,   // Overrides cached tag check to select a specific way and set for writeback
   input  logic                        SelCMOWriteback,// Overrides cached tag check to select a specific way and set for writeback for both data and tag
@@ -80,30 +81,18 @@ module cacheway import cvw::*; #(parameter cvw_t P,
   logic                               SelData;
   logic                               SelNotHit2;
   
-  if (P.ZICBOZ_SUPPORTED) begin : cbologic
-    assign SelNotHit2 = SetValid & ~CMOZeroHit;
-    //assign SelNotHit2 = SetValid;
-    
-  end else begin : cbologic
-    assign SelNotHit2 = SetValid;
-  end
-
   if (!READ_ONLY_CACHE) begin:flushlogic
     logic                               FlushWayEn;
-
     mux2 #(1) seltagmux(VictimWay, FlushWay, SelFlush, SelTag);
 
     // FlushWay is part of a one hot way selection. Must clear it if FlushWay not selected.
     // coverage off -item e 1 -fecexprrow 3
     // nonzero ways will never see SelFlush=0 while FlushWay=1 since FlushWay only advances on a subset of SelFlush assertion cases.
     assign FlushWayEn = FlushWay & SelFlush;
-    // *** RT: This is slopy. I should refactor to have the fsm issue two types of writeback commands
+    assign SelNonHit = FlushWayEn | SelWay; 
-    assign SelNonHit = FlushWayEn | SelNotHit2 | SelWriteback; // *** this is not correct
-
-    //assign SelNonHit = FlushWayEn | SelNotHit2 | SelWriteback;
   end else begin:flushlogic // no flush operation for read-only caches.
     assign SelTag = VictimWay;
-    assign SelNonHit = SelNotHit2;
+    assign SelNonHit = SelWay;
   end
 
   mux2 #(1) selectedwaymux(HitWay, SelTag, SelNonHit , SelData);