From 731e1fe08f32fd04271b4a56203b3dfa8851ec14 Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Sun, 2 Jun 2024 15:48:42 -0500 Subject: [PATCH] Updated spill logic to reflect changes in textbook. --- src/ifu/ifu.sv | 2 +- src/ifu/spill.sv | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/ifu/ifu.sv b/src/ifu/ifu.sv index 9bb54e1a0..302b88078 100644 --- a/src/ifu/ifu.sv +++ b/src/ifu/ifu.sv @@ -148,7 +148,7 @@ module ifu import cvw::*; #(parameter cvw_t P) ( ///////////////////////////////////////////////////////////////////////////////////////////// if(P.ZCA_SUPPORTED) begin : Spill - spill #(P) spill(.clk, .reset, .StallD, .FlushD, .PCF, .PCPlus4F, .PCNextF, .InstrRawF, .InstrUpdateDAF, .CacheableF, + spill #(P) spill(.clk, .reset, .StallF, .FlushD, .PCF, .PCPlus4F, .PCNextF, .InstrRawF, .InstrUpdateDAF, .CacheableF, .IFUCacheBusStallF, .ITLBMissF, .PCSpillNextF, .PCSpillF, .SelSpillNextF, .PostSpillInstrRawF, .CompressedF); end else begin : NoSpill assign PCSpillNextF = PCNextF; diff --git a/src/ifu/spill.sv b/src/ifu/spill.sv index 122efff1c..49e4ddc82 100644 --- a/src/ifu/spill.sv +++ b/src/ifu/spill.sv @@ -33,7 +33,7 @@ module spill import cvw::*; #(parameter cvw_t P) ( input logic clk, input logic reset, - input logic StallD, FlushD, + input logic StallF, FlushD, input logic [P.XLEN-1:0] PCF, // 2 byte aligned PC in Fetch stage input logic [P.XLEN-1:2] PCPlus4F, // PCF + 4 input logic [P.XLEN-1:0] PCNextF, // The next PCF @@ -96,7 +96,7 @@ module spill import cvw::*; #(parameter cvw_t P) ( case (CurrState) STATE_READY: if (TakeSpillF) NextState = STATE_SPILL; else NextState = STATE_READY; - STATE_SPILL: if(StallD) NextState = STATE_SPILL; + STATE_SPILL: if(StallF) NextState = STATE_SPILL; else NextState = STATE_READY; default: NextState = STATE_READY; endcase