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https://github.com/openhwgroup/cvw
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APB CLINT passing regression
This commit is contained in:
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5f5ad77d4a
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72e216d053
@ -49,6 +49,8 @@ module ahblite (
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input logic [2:0] IFUBurstType,
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input logic [2:0] IFUBurstType,
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input logic [1:0] IFUTransType,
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input logic [1:0] IFUTransType,
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input logic IFUTransComplete,
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input logic IFUTransComplete,
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input logic [(`XLEN-1)/8:0] ByteMaskM,
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// Signals from Data Cache
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// Signals from Data Cache
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input logic [`PA_BITS-1:0] LSUBusAdr,
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input logic [`PA_BITS-1:0] LSUBusAdr,
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input logic LSUBusRead,
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input logic LSUBusRead,
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@ -67,6 +69,7 @@ module ahblite (
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(* mark_debug = "true" *) output logic HCLK, HRESETn,
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(* mark_debug = "true" *) output logic HCLK, HRESETn,
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(* mark_debug = "true" *) output logic [31:0] HADDR, // *** one day switch to a different bus that supports the full physical address
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(* mark_debug = "true" *) output logic [31:0] HADDR, // *** one day switch to a different bus that supports the full physical address
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(* mark_debug = "true" *) output logic [`AHBW-1:0] HWDATA,
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(* mark_debug = "true" *) output logic [`AHBW-1:0] HWDATA,
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output logic [`XLEN/8-1:0] HWSTRB,
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(* mark_debug = "true" *) output logic HWRITE,
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(* mark_debug = "true" *) output logic HWRITE,
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(* mark_debug = "true" *) output logic [2:0] HSIZE,
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(* mark_debug = "true" *) output logic [2:0] HSIZE,
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(* mark_debug = "true" *) output logic [2:0] HBURST,
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(* mark_debug = "true" *) output logic [2:0] HBURST,
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@ -154,6 +157,7 @@ module ahblite (
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assign HTRANS = (GrantData) ? LSUTransType : IFUTransType; // SEQ if not first read or write, NONSEQ if first read or write, IDLE otherwise
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assign HTRANS = (GrantData) ? LSUTransType : IFUTransType; // SEQ if not first read or write, NONSEQ if first read or write, IDLE otherwise
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assign HMASTLOCK = 0; // no locking supported
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assign HMASTLOCK = 0; // no locking supported
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assign HWRITE = (NextBusState == MEMWRITE);
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assign HWRITE = (NextBusState == MEMWRITE);
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assign HWSTRB = ByteMaskM;
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// delay write data by one cycle for
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// delay write data by one cycle for
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flopen #(`XLEN) wdreg(HCLK, (LSUBusAck | LSUBusInit), LSUBusHWDATA, HWDATA); // delay HWDATA by 1 cycle per spec; *** assumes AHBW = XLEN
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flopen #(`XLEN) wdreg(HCLK, (LSUBusAck | LSUBusInit), LSUBusHWDATA, HWDATA); // delay HWDATA by 1 cycle per spec; *** assumes AHBW = XLEN
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// delay signals for subword writes
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// delay signals for subword writes
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@ -77,6 +77,8 @@ module lsu (
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(* mark_debug = "true" *) output logic [2:0] LSUBurstType,
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(* mark_debug = "true" *) output logic [2:0] LSUBurstType,
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(* mark_debug = "true" *) output logic [1:0] LSUTransType,
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(* mark_debug = "true" *) output logic [1:0] LSUTransType,
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(* mark_debug = "true" *) output logic LSUTransComplete,
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(* mark_debug = "true" *) output logic LSUTransComplete,
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output logic [(`XLEN-1)/8:0] ByteMaskM,
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// page table walker
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// page table walker
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input logic [`XLEN-1:0] SATP_REGW, // from csr
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input logic [`XLEN-1:0] SATP_REGW, // from csr
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input logic STATUS_MXR, STATUS_SUM, STATUS_MPRV,
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input logic STATUS_MXR, STATUS_SUM, STATUS_MPRV,
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@ -112,7 +114,6 @@ module lsu (
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logic LSUBusWriteCrit;
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logic LSUBusWriteCrit;
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logic DataDAPageFaultM;
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logic DataDAPageFaultM;
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logic [`XLEN-1:0] LSUWriteDataM;
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logic [`XLEN-1:0] LSUWriteDataM;
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logic [(`XLEN-1)/8:0] ByteMaskM;
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logic [`XLEN-1:0] WriteDataM;
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logic [`XLEN-1:0] WriteDataM;
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logic [`LLEN-1:0] ReadDataM;
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logic [`LLEN-1:0] ReadDataM;
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@ -268,10 +269,10 @@ module lsu (
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/////////////////////////////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////////////////////////////
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// Subword Accesses
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// Subword Accesses
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/////////////////////////////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////////////////////////////
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subwordwrite subwordwrite(.LSUPAdrM(LSUPAdrM[2:0]),
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.LSUFunct3M, .AMOWriteDataM, .LittleEndianWriteDataM, .ByteMaskM);
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subwordread subwordread(.ReadDataWordMuxM, .LSUPAdrM(LSUPAdrM[2:0]),
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subwordread subwordread(.ReadDataWordMuxM, .LSUPAdrM(LSUPAdrM[2:0]),
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.FpLoadStoreM, .Funct3M(LSUFunct3M), .ReadDataM);
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.FpLoadStoreM, .Funct3M(LSUFunct3M), .ReadDataM);
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subwordwrite subwordwrite(.LSUPAdrM(LSUPAdrM[2:0]),
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.LSUFunct3M, .AMOWriteDataM, .LittleEndianWriteDataM, .ByteMaskM);
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/////////////////////////////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////////////////////////////
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// MW Pipeline Register
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// MW Pipeline Register
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@ -34,10 +34,10 @@ module ahbapbbridge #(PERIPHS = 2) (
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input logic [PERIPHS-1:0] HSEL,
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input logic [PERIPHS-1:0] HSEL,
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input logic [31:0] HADDR,
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input logic [31:0] HADDR,
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input logic [`XLEN-1:0] HWDATA,
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input logic [`XLEN-1:0] HWDATA,
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input logic [`XLEN/8-1:0] HWSTRB,
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input logic HWRITE,
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input logic HWRITE,
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input logic [1:0] HTRANS,
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input logic [1:0] HTRANS,
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input logic HREADY,
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input logic HREADY,
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input logic [`XLEN/8-1:0] HWSTRB,
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// input logic [3:0] HPROT, // not used
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// input logic [3:0] HPROT, // not used
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output logic [`XLEN-1:0] HRDATA,
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output logic [`XLEN-1:0] HRDATA,
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output logic HRESP, HREADYOUT,
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output logic HRESP, HREADYOUT,
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@ -102,7 +102,7 @@ module ahbapbbridge #(PERIPHS = 2) (
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end
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end
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end
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end
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end
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end
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assign HREADYOUT = PREADYOUT & PENABLE; // don't raise HREADYOUT until access phase
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assign HREADYOUT = PREADYOUT & ~initTransSelD; // don't raise HREADYOUT before access phase
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// resp logic
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// resp logic
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assign HRESP = 0; // bridge never indicates errors
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assign HRESP = 0; // bridge never indicates errors
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@ -28,7 +28,7 @@
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// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
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// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
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// OR OTHER DEALINGS IN THE SOFTWARE.
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// OR OTHER DEALINGS IN THE SOFTWARE.
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////////////////////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////////////////////
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/*
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`include "wally-config.vh"
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`include "wally-config.vh"
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module clint (
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module clint (
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@ -258,3 +258,4 @@ module graytobinary #(parameter N = `XLEN) (
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assign b[i] = g[i] ^ b[i+1];
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assign b[i] = g[i] ^ b[i+1];
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end
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end
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endmodule
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endmodule
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*/
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252
pipelined/src/uncore/clint_apb.sv
Normal file
252
pipelined/src/uncore/clint_apb.sv
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@ -0,0 +1,252 @@
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///////////////////////////////////////////
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// clint_apb.sv
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//
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// Written: David_Harris@hmc.edu 14 January 2021
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// Modified:
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//
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// Purpose: Core-Local Interruptor
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// See FE310-G002-Manual-v19p05 for specifications
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// MIT LICENSE
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this
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// software and associated documentation files (the "Software"), to deal in the Software
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// without restriction, including without limitation the rights to use, copy, modify, merge,
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// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons
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// to whom the Software is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or
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// substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
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// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
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// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
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// OR OTHER DEALINGS IN THE SOFTWARE.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module clint_apb (
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input logic PCLK, PRESETn,
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input logic PSEL,
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input logic [15:0] PADDR,
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input logic [`XLEN-1:0] PWDATA,
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input logic [`XLEN/8-1:0] PSTRB,
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input logic PWRITE,
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input logic PENABLE,
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output logic [`XLEN-1:0] PRDATA,
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output logic PREADY,
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(* mark_debug = "true" *) output logic [63:0] MTIME,
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output logic MTimerInt, MSwInt);
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logic MSIP;
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logic [15:0] entry;
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logic memwrite;
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(* mark_debug = "true" *) logic [63:0] MTIMECMP;
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integer i, j;
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assign memwrite = PWRITE & PENABLE & PSEL; // only write in access phase
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assign PREADY = 1'b1; // GPIO never takes >1 cycle to respond
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// word aligned reads
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if (`XLEN==64) assign #2 entry = {PADDR[15:3], 3'b000};
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else assign #2 entry = {PADDR[15:2], 2'b00};
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//swbytemask swbytemask(.Size(HSIZED[1:0]), .Adr(entry[2:0]), .ByteMask(PSTRB));
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// DH 2/20/21: Eventually allow MTIME to run off a separate clock
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// This will require synchronizing MTIME to the system clock
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// before it is read or compared to MTIMECMP.
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// It will also require synchronizing the write to MTIMECMP.
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// Use req and ack signals synchronized across the clock domains.
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// register access
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if (`XLEN==64) begin:clint // 64-bit
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always @(posedge PCLK) begin
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case(entry)
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16'h0000: PRDATA <= {63'b0, MSIP};
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16'h4000: PRDATA <= MTIMECMP;
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16'hBFF8: PRDATA <= MTIME;
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default: PRDATA <= 0;
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endcase
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end
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always_ff @(posedge PCLK or negedge PRESETn)
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if (~PRESETn) begin
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MSIP <= 0;
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MTIMECMP <= 64'hFFFFFFFFFFFFFFFF; // Spec says MTIMECMP is not reset, but we reset to maximum value to prevent spurious timer interrupts
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end else if (memwrite) begin
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if (entry == 16'h0000) MSIP <= PWDATA[0];
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if (entry == 16'h4000) begin
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for(i=0;i<`XLEN/8;i++)
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if(PSTRB[i])
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MTIMECMP[i*8 +: 8] <= PWDATA[i*8 +: 8]; // ***dh: this notation isn't in book yet - maybe from Ross
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end
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end
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// eventually replace MTIME logic below with timereg
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// timereg tr(PCLK, PRESETn, TIMECLK, memwrite & (entry==16'hBFF8), 1'b0, PWDATA, MTIME, done);
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always_ff @(posedge PCLK or negedge PRESETn)
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if (~PRESETn) begin
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MTIME <= 0;
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end else if (memwrite & entry == 16'hBFF8) begin
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// MTIME Counter. Eventually change this to run off separate clock. Synchronization then needed
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for(j=0;j<`XLEN/8;j++)
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if(PSTRB[j])
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MTIME[j*8 +: 8] <= PWDATA[j*8 +: 8];
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end else MTIME <= MTIME + 1;
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end else begin:clint // 32-bit
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always @(posedge PCLK) begin
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case(entry)
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16'h0000: PRDATA <= {31'b0, MSIP};
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16'h4000: PRDATA <= MTIMECMP[31:0];
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16'h4004: PRDATA <= MTIMECMP[63:32];
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16'hBFF8: PRDATA <= MTIME[31:0];
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16'hBFFC: PRDATA <= MTIME[63:32];
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default: PRDATA <= 0;
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endcase
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end
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always_ff @(posedge PCLK or negedge PRESETn)
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if (~PRESETn) begin
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MSIP <= 0;
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MTIMECMP <= 0;
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// MTIMECMP is not reset ***?
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end else if (memwrite) begin
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if (entry == 16'h0000) MSIP <= PWDATA[0];
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if (entry == 16'h4000)
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for(j=0;j<`XLEN/8;j++)
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if(PSTRB[j])
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MTIMECMP[j*8 +: 8] <= PWDATA[j*8 +: 8];
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if (entry == 16'h4004)
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for(j=0;j<`XLEN/8;j++)
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if(PSTRB[j])
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MTIMECMP[32 + j*8 +: 8] <= PWDATA[j*8 +: 8];
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// MTIME Counter. Eventually change this to run off separate clock. Synchronization then needed
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end
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// eventually replace MTIME logic below with timereg
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// timereg tr(PCLK, PRESETn, TIMECLK, memwrite & (entry==16'hBFF8), memwrite & (entry == 16'hBFFC), PWDATA, MTIME, done);
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always_ff @(posedge PCLK or negedge PRESETn)
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if (~PRESETn) begin
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MTIME <= 0;
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// MTIMECMP is not reset
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end else if (memwrite & (entry == 16'hBFF8)) begin
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for(i=0;i<`XLEN/8;i++)
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if(PSTRB[i])
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MTIME[i*8 +: 8] <= PWDATA[i*8 +: 8];
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end else if (memwrite & (entry == 16'hBFFC)) begin
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// MTIME Counter. Eventually change this to run off separate clock. Synchronization then needed
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for(i=0;i<`XLEN/8;i++)
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if(PSTRB[i])
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MTIME[32 + i*8 +: 8]<= PWDATA[i*8 +: 8];
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end else MTIME <= MTIME + 1;
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end
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// Software interrupt when MSIP is set
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assign MSwInt = MSIP;
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// Timer interrupt when MTIME >= MTIMECMP
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assign MTimerInt = ({1'b0, MTIME} >= {1'b0, MTIMECMP}); // unsigned comparison
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endmodule
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module timeregsync(
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input logic clk, resetn,
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input logic we0, we1,
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input logic [`XLEN-1:0] wd,
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output logic [63:0] q);
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if (`XLEN==64)
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always_ff @(posedge clk or negedge resetn)
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if (~resetn) q <= 0;
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else if (we0) q <= wd;
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else q <= q + 1;
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else
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always_ff @(posedge clk or negedge resetn)
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if (~resetn) q <= 0;
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else if (we0) q[31:0] <= wd;
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else if (we1) q[63:32] <= wd;
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else q <= q + 1;
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endmodule
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module timereg(
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input logic PCLK, PRESETn, TIMECLK,
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input logic we0, we1,
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input logic [`XLEN-1:0] PWDATA,
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output logic [63:0] MTIME,
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output logic done);
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// if (`TIMEBASE_SYNC) begin:timereg // use PCLK for MTIME
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if (1) begin:timereg // use PCLK for MTIME
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timregsync timeregsync(.clk(PCLK), .resetn(PRESETn), .we0, .we1, .wd(PWDATA), .q(MTIME));
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assign done = 1; // immediately completes
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end else begin // use asynchronous TIMECLK
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// TIME counter runs on TIMECLK but bus interface runs on PCLK
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// Need to synchronize reads and writes
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// This is subtle because synchronizing a binary counter on a per-bit basis could give a mix of old and new bits
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// Instead, we use a Gray coded counter that only changes one bit per cycle
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// Synchronizing this for a read is safe because we are guaranteed to get either the old or the new value.
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// Writing to the counter requires a request/acknowledge handshake to ensure the write value is held long enough.
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// The handshake signals are synchronized in each direction across the interface
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// There is no back pressure on instructions, so if multiple counter writes occur ***
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logic req, req_sync, ack, we0_stored, we1_stored, ack_stored, resetn_sync;
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logic [`XLEN-1:0] wd_stored;
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logic [63:0] time_int, time_int_gc, time_gc, MTIME_GC;
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// When a write enable is asserted for a cycle, sample the enables and data and raise a request until it is acknowledged
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// When the acknowledge falls, the transaction is done and the system is ready for another write.
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||||||
|
// ***look at redoing this assuming write enable and data are held rather than pulsed.
|
||||||
|
always_ff @(posedge PCLK or negedge PRESETn)
|
||||||
|
if (~PRESETn)
|
||||||
|
req <= 0; // don't bother resetting wd
|
||||||
|
else begin
|
||||||
|
req <= we0 | we1 | req & ~ack;
|
||||||
|
we0_stored <= we0;
|
||||||
|
we1_stored <= we1;
|
||||||
|
wd_stored <= PWDATA;
|
||||||
|
ack_stored <= ack;
|
||||||
|
done <= ack_stored & ~ack;
|
||||||
|
end
|
||||||
|
|
||||||
|
// synchronize the reset and reqest into the TIMECLK domain
|
||||||
|
sync resetsync(TIMECLK, PRESETn, resetn_sync);
|
||||||
|
sync rsync(TIMECLK, req, req_sync);
|
||||||
|
// synchronize the acknowledge back to the PCLK domain to indicate the request was handled and can be lowered
|
||||||
|
sync async(PCLK, req_sync, ack);
|
||||||
|
|
||||||
|
timeregsync timeregsync(.clk(TIMECLK), .resetn(resetn_sync), .we0(we0_stored), .we1(we1_stored), .wd(wd_stored), .q(time_int));
|
||||||
|
binarytogray b2g(time_int, time_int_gc);
|
||||||
|
flop gcreg(TIMECLK, time_int_gc, time_gc);
|
||||||
|
|
||||||
|
sync timesync[63:0](PCLK, time_gc, MTIME_GC);
|
||||||
|
graytobinary g2b(MTIME_GC, MTIME);
|
||||||
|
end
|
||||||
|
endmodule
|
||||||
|
|
||||||
|
module binarytogray #(parameter N = `XLEN) (
|
||||||
|
input logic [N-1:0] b,
|
||||||
|
output logic [N-1:0] g);
|
||||||
|
|
||||||
|
// G[N-1] = B[N-1]; G[i] = B[i] ^ B[i+1] for 0 <= i < N-1
|
||||||
|
// requires single layer of N-1 XOR gates
|
||||||
|
assign g = b ^ {1'b0, b[N-1:1]};
|
||||||
|
endmodule
|
||||||
|
|
||||||
|
module graytobinary #(parameter N = `XLEN) (
|
||||||
|
input logic [N-1:0] g,
|
||||||
|
output logic [N-1:0] b);
|
||||||
|
|
||||||
|
// B[N-1] = G[N-1]; B[i] = G[i] ^ B[i+1] for 0 <= i < N-1
|
||||||
|
// requires rippling through N-1 XOR gates
|
||||||
|
genvar i;
|
||||||
|
assign b[N-1] = g[N-1];
|
||||||
|
for (i=N-2; i >= 0; i--) begin:g2b
|
||||||
|
assign b[i] = g[i] ^ b[i+1];
|
||||||
|
end
|
||||||
|
endmodule
|
@ -39,6 +39,7 @@ module uncore (
|
|||||||
input logic TIMECLK,
|
input logic TIMECLK,
|
||||||
input logic [31:0] HADDR,
|
input logic [31:0] HADDR,
|
||||||
input logic [`AHBW-1:0] HWDATA,
|
input logic [`AHBW-1:0] HWDATA,
|
||||||
|
input logic [`XLEN/8-1:0] HWSTRB,
|
||||||
input logic HWRITE,
|
input logic HWRITE,
|
||||||
input logic [2:0] HSIZE,
|
input logic [2:0] HSIZE,
|
||||||
input logic [2:0] HBURST,
|
input logic [2:0] HBURST,
|
||||||
@ -93,8 +94,6 @@ module uncore (
|
|||||||
logic HRESPBRIDGE, HREADYBRIDGE, HSELBRIDGE, HSELBRIDGED;
|
logic HRESPBRIDGE, HREADYBRIDGE, HSELBRIDGE, HSELBRIDGED;
|
||||||
|
|
||||||
// *** to do:
|
// *** to do:
|
||||||
// combinational loop related to HREADY, HREADYOUT through PENABLE
|
|
||||||
// hook up and test GPIO on AHB
|
|
||||||
// hook up HWSTRB and remove subword write decoders
|
// hook up HWSTRB and remove subword write decoders
|
||||||
// add other peripherals on AHB
|
// add other peripherals on AHB
|
||||||
// HTRANS encoding
|
// HTRANS encoding
|
||||||
@ -109,13 +108,10 @@ module uncore (
|
|||||||
|
|
||||||
// AHB -> APB bridge
|
// AHB -> APB bridge
|
||||||
ahbapbbridge #(2) ahbapbbridge
|
ahbapbbridge #(2) ahbapbbridge
|
||||||
(.HCLK, .HRESETn, .HSEL({1'b0, HSELGPIO}), .HADDR, .HWDATA, .HWRITE, .HTRANS, .HREADY, .HWSTRB('1),
|
(.HCLK, .HRESETn, .HSEL({HSELCLINT, HSELGPIO}), .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HTRANS, .HREADY,
|
||||||
.HRDATA(HREADBRIDGE), .HRESP(HRESPBRIDGE), .HREADYOUT(HREADYBRIDGE),
|
.HRDATA(HREADBRIDGE), .HRESP(HRESPBRIDGE), .HREADYOUT(HREADYBRIDGE),
|
||||||
.PCLK, .PRESETn, .PSEL, .PWRITE, .PENABLE, .PADDR, .PWDATA, .PSTRB, .PREADY, .PRDATA);
|
.PCLK, .PRESETn, .PSEL, .PWRITE, .PENABLE, .PADDR, .PWDATA, .PSTRB, .PREADY, .PRDATA);
|
||||||
assign PREADY[1] = 0; // *** replace these with connections to other peripherals
|
assign HSELBRIDGE = HSELGPIO | HSELCLINT; // if any of the bridge signals are selected
|
||||||
assign PRDATA[1] = 0;
|
|
||||||
assign HSELBRIDGE = HSELGPIO; // if any of the bridge signals are selected
|
|
||||||
// This system is showing a combinatonal loop related to HREADY and HREADYBRIDGE and HREADYGPIO
|
|
||||||
|
|
||||||
// on-chip RAM
|
// on-chip RAM
|
||||||
if (`RAM_SUPPORTED) begin : ram
|
if (`RAM_SUPPORTED) begin : ram
|
||||||
@ -140,13 +136,18 @@ module uncore (
|
|||||||
|
|
||||||
// memory-mapped I/O peripherals
|
// memory-mapped I/O peripherals
|
||||||
if (`CLINT_SUPPORTED == 1) begin : clint
|
if (`CLINT_SUPPORTED == 1) begin : clint
|
||||||
clint clint(
|
/* clint clint(
|
||||||
.HCLK, .HRESETn, .TIMECLK,
|
.HCLK, .HRESETn, .TIMECLK,
|
||||||
.HSELCLINT, .HADDR(HADDR[15:0]), .HWRITE,
|
.HSELCLINT, .HADDR(HADDR[15:0]), .HWRITE,
|
||||||
.HWDATA, .HREADY, .HTRANS, .HSIZED,
|
.HWDATA, .HREADY, .HTRANS, .HSIZED,
|
||||||
.HREADCLINT,
|
.HREADCLINT,
|
||||||
.HRESPCLINT, .HREADYCLINT,
|
.HRESPCLINT, .HREADYCLINT,
|
||||||
.MTIME(MTIME_CLINT),
|
.MTIME(MTIME_CLINT),
|
||||||
|
.MTimerInt, .MSwInt);*/
|
||||||
|
clint_apb clint(
|
||||||
|
.PCLK, .PRESETn, .PSEL(PSEL[1]), .PADDR(PADDR[15:0]), .PWDATA, .PSTRB, .PWRITE, .PENABLE,
|
||||||
|
.PRDATA(PRDATA[1]), .PREADY(PREADY[1]),
|
||||||
|
.MTIME(MTIME_CLINT),
|
||||||
.MTimerInt, .MSwInt);
|
.MTimerInt, .MSwInt);
|
||||||
|
|
||||||
end else begin : clint
|
end else begin : clint
|
||||||
@ -215,7 +216,7 @@ module uncore (
|
|||||||
// AHB Read Multiplexer
|
// AHB Read Multiplexer
|
||||||
assign HRDATA = ({`XLEN{HSELRamD}} & HREADRam) |
|
assign HRDATA = ({`XLEN{HSELRamD}} & HREADRam) |
|
||||||
({`XLEN{HSELEXTD}} & HRDATAEXT) |
|
({`XLEN{HSELEXTD}} & HRDATAEXT) |
|
||||||
({`XLEN{HSELCLINTD}} & HREADCLINT) |
|
// ({`XLEN{HSELCLINTD}} & HREADCLINT) |
|
||||||
({`XLEN{HSELPLICD}} & HREADPLIC) |
|
({`XLEN{HSELPLICD}} & HREADPLIC) |
|
||||||
// ({`XLEN{HSELGPIOD}} & HREADGPIO) |
|
// ({`XLEN{HSELGPIOD}} & HREADGPIO) |
|
||||||
({`XLEN{HSELBRIDGED}} & HREADBRIDGE) |
|
({`XLEN{HSELBRIDGED}} & HREADBRIDGE) |
|
||||||
@ -225,7 +226,7 @@ module uncore (
|
|||||||
|
|
||||||
assign HRESP = HSELRamD & HRESPRam |
|
assign HRESP = HSELRamD & HRESPRam |
|
||||||
HSELEXTD & HRESPEXT |
|
HSELEXTD & HRESPEXT |
|
||||||
HSELCLINTD & HRESPCLINT |
|
// HSELCLINTD & HRESPCLINT |
|
||||||
HSELPLICD & HRESPPLIC |
|
HSELPLICD & HRESPPLIC |
|
||||||
// HSELGPIOD & HRESPGPIO |
|
// HSELGPIOD & HRESPGPIO |
|
||||||
HSELBRIDGE & HRESPBRIDGE |
|
HSELBRIDGE & HRESPBRIDGE |
|
||||||
@ -235,7 +236,7 @@ module uncore (
|
|||||||
|
|
||||||
assign HREADY = HSELRamD & HREADYRam |
|
assign HREADY = HSELRamD & HREADYRam |
|
||||||
HSELEXTD & HREADYEXT |
|
HSELEXTD & HREADYEXT |
|
||||||
HSELCLINTD & HREADYCLINT |
|
// HSELCLINTD & HREADYCLINT |
|
||||||
HSELPLICD & HREADYPLIC |
|
HSELPLICD & HREADYPLIC |
|
||||||
// HSELGPIOD & HREADYGPIO |
|
// HSELGPIOD & HREADYGPIO |
|
||||||
HSELBRIDGED & HREADYBRIDGE |
|
HSELBRIDGED & HREADYBRIDGE |
|
||||||
@ -244,6 +245,8 @@ module uncore (
|
|||||||
HSELSDCD & HREADYSDC |
|
HSELSDCD & HREADYSDC |
|
||||||
HSELNoneD; // don't lock up the bus if no region is being accessed
|
HSELNoneD; // don't lock up the bus if no region is being accessed
|
||||||
|
|
||||||
|
// *** remove HREADYGPIO, others
|
||||||
|
|
||||||
// Address Decoder Delay (figure 4-2 in spec)
|
// Address Decoder Delay (figure 4-2 in spec)
|
||||||
flopr #(9) hseldelayreg(HCLK, ~HRESETn, HSELRegions, {HSELNoneD, HSELEXTD, HSELBootRomD, HSELRamD, HSELCLINTD, HSELGPIOD, HSELUARTD, HSELPLICD, HSELSDCD});
|
flopr #(9) hseldelayreg(HCLK, ~HRESETn, HSELRegions, {HSELNoneD, HSELEXTD, HSELBootRomD, HSELRamD, HSELCLINTD, HSELGPIOD, HSELUARTD, HSELPLICD, HSELSDCD});
|
||||||
flopr #(1) hselbridgedelayreg(HCLK, ~HRESETn, HSELBRIDGE, HSELBRIDGED);
|
flopr #(1) hselbridgedelayreg(HCLK, ~HRESETn, HSELBRIDGE, HSELBRIDGED);
|
||||||
|
@ -42,6 +42,7 @@ module wallypipelinedcore (
|
|||||||
output logic HCLK, HRESETn,
|
output logic HCLK, HRESETn,
|
||||||
output logic [31:0] HADDR,
|
output logic [31:0] HADDR,
|
||||||
output logic [`AHBW-1:0] HWDATA,
|
output logic [`AHBW-1:0] HWDATA,
|
||||||
|
output logic [`XLEN/8-1:0] HWSTRB,
|
||||||
output logic HWRITE,
|
output logic HWRITE,
|
||||||
output logic [2:0] HSIZE,
|
output logic [2:0] HSIZE,
|
||||||
output logic [2:0] HBURST,
|
output logic [2:0] HBURST,
|
||||||
@ -115,6 +116,8 @@ module wallypipelinedcore (
|
|||||||
logic [1:0] PageType;
|
logic [1:0] PageType;
|
||||||
logic sfencevmaM, wfiM, IntPendingM;
|
logic sfencevmaM, wfiM, IntPendingM;
|
||||||
logic SelHPTW;
|
logic SelHPTW;
|
||||||
|
logic [`XLEN/8-1:0] ByteMaskM;
|
||||||
|
|
||||||
|
|
||||||
// PMA checker signals
|
// PMA checker signals
|
||||||
var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [`PMP_ENTRIES-1:0];
|
var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [`PMP_ENTRIES-1:0];
|
||||||
@ -263,6 +266,7 @@ module wallypipelinedcore (
|
|||||||
// connected to ahb (all stay the same)
|
// connected to ahb (all stay the same)
|
||||||
.LSUBusAdr, .LSUBusRead, .LSUBusWrite, .LSUBusAck, .LSUBusInit,
|
.LSUBusAdr, .LSUBusRead, .LSUBusWrite, .LSUBusAck, .LSUBusInit,
|
||||||
.LSUBusHRDATA, .LSUBusHWDATA, .LSUBusSize, .LSUBurstType, .LSUTransType, .LSUTransComplete,
|
.LSUBusHRDATA, .LSUBusHWDATA, .LSUBusSize, .LSUBurstType, .LSUTransType, .LSUTransComplete,
|
||||||
|
.ByteMaskM,
|
||||||
|
|
||||||
// connect to csr or privilege and stay the same.
|
// connect to csr or privilege and stay the same.
|
||||||
.PrivilegeModeW, .BigEndianM, // connects to csr
|
.PrivilegeModeW, .BigEndianM, // connects to csr
|
||||||
@ -309,9 +313,10 @@ module wallypipelinedcore (
|
|||||||
.LSUTransComplete,
|
.LSUTransComplete,
|
||||||
.LSUBusAck,
|
.LSUBusAck,
|
||||||
.LSUBusInit,
|
.LSUBusInit,
|
||||||
|
.ByteMaskM,
|
||||||
|
|
||||||
.HRDATA, .HREADY, .HRESP, .HCLK, .HRESETn,
|
.HRDATA, .HREADY, .HRESP, .HCLK, .HRESETn,
|
||||||
.HADDR, .HWDATA, .HWRITE, .HSIZE, .HBURST,
|
.HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST,
|
||||||
.HPROT, .HTRANS, .HMASTLOCK, .HADDRD, .HSIZED,
|
.HPROT, .HTRANS, .HMASTLOCK, .HADDRD, .HSIZED,
|
||||||
.HWRITED);
|
.HWRITED);
|
||||||
|
|
||||||
|
@ -48,6 +48,7 @@ module wallypipelinedsoc (
|
|||||||
output logic HCLK, HRESETn,
|
output logic HCLK, HRESETn,
|
||||||
output logic [31:0] HADDR,
|
output logic [31:0] HADDR,
|
||||||
output logic [`AHBW-1:0] HWDATA,
|
output logic [`AHBW-1:0] HWDATA,
|
||||||
|
output logic [`XLEN/8-1:0] HWSTRB,
|
||||||
output logic HWRITE,
|
output logic HWRITE,
|
||||||
output logic [2:0] HSIZE,
|
output logic [2:0] HSIZE,
|
||||||
output logic [2:0] HBURST,
|
output logic [2:0] HBURST,
|
||||||
@ -79,6 +80,7 @@ module wallypipelinedsoc (
|
|||||||
logic [3:0] HSIZED;
|
logic [3:0] HSIZED;
|
||||||
logic HWRITED;
|
logic HWRITED;
|
||||||
|
|
||||||
|
|
||||||
// synchronize reset to SOC clock domain
|
// synchronize reset to SOC clock domain
|
||||||
synchronizer resetsync(.clk, .d(reset_ext), .q(reset));
|
synchronizer resetsync(.clk, .d(reset_ext), .q(reset));
|
||||||
|
|
||||||
@ -86,13 +88,13 @@ module wallypipelinedsoc (
|
|||||||
wallypipelinedcore core(.clk, .reset,
|
wallypipelinedcore core(.clk, .reset,
|
||||||
.MTimerInt, .MExtInt, .SExtInt, .MSwInt,
|
.MTimerInt, .MExtInt, .SExtInt, .MSwInt,
|
||||||
.MTIME_CLINT,
|
.MTIME_CLINT,
|
||||||
.HRDATA, .HREADY, .HRESP, .HCLK, .HRESETn, .HADDR, .HWDATA,
|
.HRDATA, .HREADY, .HRESP, .HCLK, .HRESETn, .HADDR, .HWDATA, .HWSTRB,
|
||||||
.HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK,
|
.HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK,
|
||||||
.HADDRD, .HSIZED, .HWRITED
|
.HADDRD, .HSIZED, .HWRITED
|
||||||
);
|
);
|
||||||
|
|
||||||
uncore uncore(.HCLK, .HRESETn, .TIMECLK,
|
uncore uncore(.HCLK, .HRESETn, .TIMECLK,
|
||||||
.HADDR, .HWDATA, .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, .HRDATAEXT,
|
.HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, .HRDATAEXT,
|
||||||
.HREADYEXT, .HRESPEXT, .HRDATA, .HREADY, .HRESP, .HADDRD, .HSIZED, .HWRITED,
|
.HREADYEXT, .HRESPEXT, .HRDATA, .HREADY, .HRESP, .HADDRD, .HSIZED, .HWRITED,
|
||||||
.MTimerInt, .MSwInt, .MExtInt, .SExtInt, .GPIOPinsIn, .GPIOPinsOut, .GPIOPinsEn, .UARTSin, .UARTSout, .MTIME_CLINT,
|
.MTimerInt, .MSwInt, .MExtInt, .SExtInt, .GPIOPinsIn, .GPIOPinsOut, .GPIOPinsEn, .UARTSin, .UARTSout, .MTIME_CLINT,
|
||||||
.HSELEXT,
|
.HSELEXT,
|
||||||
|
Loading…
Reference in New Issue
Block a user