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Simplified shifter right input

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This commit is contained in:
David Harris 2021-12-18 10:25:40 -08:00
parent 7e026f3e78
commit 721d0b5bcf
2 changed files with 23 additions and 25 deletions
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4
wally-pipelined/src/ieu/alu.sv
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@ -33,7 +33,6 @@ module alu #(parameter WIDTH=32) (
output logic [WIDTH-1:0] Sum); output logic [WIDTH-1:0] Sum);
logic [WIDTH-1:0] CondInvB, Shift, SLT, SLTU, FullResult; logic [WIDTH-1:0] CondInvB, Shift, SLT, SLTU, FullResult;
logic Right;
logic Carry, Neg; logic Carry, Neg;
logic LT, LTU; logic LT, LTU;
logic Overflow; logic Overflow;
@ -51,8 +50,7 @@ module alu #(parameter WIDTH=32) (
assign {Carry, Sum} = A + CondInvB + {{(WIDTH-1){1'b0}}, SubArith}; assign {Carry, Sum} = A + CondInvB + {{(WIDTH-1){1'b0}}, SubArith};
// Shifts // Shifts
assign Right = Funct3[2]; // sra or srl shifter sh(.A, .Amt(B[`LOG_XLEN-1:0]), .Right(Funct3[2]), .Arith(SubArith), .W64, .Y(Shift));
shifter sh(A, B[`LOG_XLEN-1:0], Right, SubArith, W64, Shift);
// condition code flags based on add/subtract output // condition code flags based on add/subtract output
// Overflow occurs when the numbers being added have the same sign // Overflow occurs when the numbers being added have the same sign

42
wally-pipelined/src/ieu/shifter.sv
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@ -26,10 +26,10 @@
`include "wally-config.vh" `include "wally-config.vh"
module shifter ( module shifter (
input logic [`XLEN-1:0] a, input logic [`XLEN-1:0] A,
input logic [`LOG_XLEN-1:0] amt, input logic [`LOG_XLEN-1:0] Amt,
input logic right, arith, w64, input logic Right, Arith, W64,
output logic [`XLEN-1:0] y); output logic [`XLEN-1:0] Y);
logic [2*`XLEN-2:0] z, zshift; logic [2*`XLEN-2:0] z, zshift;
logic [`LOG_XLEN-1:0] amttrunc, offset; logic [`LOG_XLEN-1:0] amttrunc, offset;
@ -42,34 +42,34 @@ module shifter (
generate generate
if (`XLEN==32) begin:shifter // RV32 if (`XLEN==32) begin:shifter // RV32
always_comb // funnel mux always_comb // funnel mux
if (right) if (Right)
if (arith) z = {{31{a[31]}}, a}; if (Arith) z = {{31{A[31]}}, A};
else z = {31'b0, a}; else z = {31'b0, A};
else z = {a, 31'b0}; else z = {A, 31'b0};
assign amttrunc = amt; // shift amount assign amttrunc = Amt; // shift amount
end else begin:shifter // RV64 end else begin:shifter // RV64
always_comb // funnel mux always_comb // funnel mux
if (w64) begin // 32-bit shifts if (W64) begin // 32-bit shifts
if (right) if (Right)
if (arith) z = {64'b0, {31{a[31]}}, a[31:0]}; if (Arith) z = {64'b0, {31{A[31]}}, A[31:0]};
else z = {95'b0, a[31:0]}; else z = {95'b0, A[31:0]};
else z = {32'b0, a[31:0], 63'b0}; else z = {32'b0, A[31:0], 63'b0};
end else begin end else begin
if (right) if (Right)
if (arith) z = {{63{a[63]}}, a}; if (Arith) z = {{63{A[63]}}, A};
else z = {63'b0, a}; else z = {63'b0, A};
else z = {a, 63'b0}; else z = {A, 63'b0};
end end
assign amttrunc = w64 ? {1'b0, amt[4:0]} : amt; // 32 or 64-bit shift assign amttrunc = W64 ? {1'b0, Amt[4:0]} : Amt; // 32 or 64-bit shift
end end
endgenerate endgenerate
// opposite offset for right shfits // opposite offset for right shfits
assign offset = right ? amttrunc : ~amttrunc; assign offset = Right ? amttrunc : ~amttrunc;
// funnel operation // funnel operation
assign zshift = z >> offset; assign zshift = z >> offset;
assign y = zshift[`XLEN-1:0]; assign Y = zshift[`XLEN-1:0];
endmodule endmodule