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Removed int/integer from parameters)

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This commit is contained in:
David Harris 2023-01-27 14:27:04 -08:00
parent 44c7102026
commit 717cb4e6c5
12 changed files with 128 additions and 150 deletions
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8
pipelined/src/ebu/ahbcacheinterface.sv
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@ -30,10 +30,10 @@
`include "wally-config.vh"
module ahbcacheinterface #(
parameter integer BEATSPERLINE, // Number of AHBW words (beats) in cacheline
parameter integer AHBWLOGBWPL, // Log2 of ^
parameter integer LINELEN, // Number of bits in cacheline
parameter integer LLENPOVERAHBW // Number of AHB beats in a LLEN word. AHBW cannot be larger than LLEN. (implementation limitation)
parameter BEATSPERLINE, // Number of AHBW words (beats) in cacheline
parameter AHBWLOGBWPL, // Log2 of ^
parameter LINELEN, // Number of bits in cacheline
parameter LLENPOVERAHBW // Number of AHB beats in a LLEN word. AHBW cannot be larger than LLEN. (implementation limitation)
)(
input logic HCLK, HRESETn,
// bus interface controls

4
pipelined/src/ebu/buscachefsm.sv
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@ -32,8 +32,8 @@
// HCLK and clk must be the same clock!
module buscachefsm #(
parameter integer BeatCountThreshold, // Largest beat index
parameter integer AHBWLOGBWPL // Log2 of BEATSPERLINE
parameter BeatCountThreshold, // Largest beat index
parameter AHBWLOGBWPL // Log2 of BEATSPERLINE
)(
input logic HCLK,
input logic HRESETn,

6
pipelined/src/ifu/bpred/RAsPredictor.sv
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@ -28,10 +28,8 @@
`include "wally-config.vh"
module RASPredictor
#(parameter int StackSize = 16
)
(input logic clk,
module RASPredictor #(parameter StackSize = 16) (
input logic clk,
input logic reset,
input logic PopF,
output logic [`XLEN-1:0] RASPCF,

6
pipelined/src/ifu/bpred/btb.sv
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@ -30,10 +30,8 @@
`include "wally-config.vh"
module btb
#(parameter int Depth = 10
)
(input logic clk,
module btb #(parameter Depth = 10) (
input logic clk,
input logic reset,
input logic StallF, StallE,
input logic [`XLEN-1:0] PCNextF,

7
pipelined/src/ifu/bpred/foldedgshare.sv
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@ -28,11 +28,8 @@
`include "wally-config.vh"
module foldedgshare
#(parameter int k = 16,
parameter int depth = 10
)
(input logic clk,
module foldedgshare #(parameter k = 16, depth = 10) (
input logic clk,
input logic reset,
input logic StallF, StallD, StallE, StallM, StallW,
input logic FlushD, FlushE, FlushM, FlushW,

6
pipelined/src/ifu/bpred/globalhistory.sv
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@ -28,10 +28,8 @@
`include "wally-config.vh"
module globalhistory
#(parameter int k = 10
)
(input logic clk,
module globalhistory #(parameter k = 10) (
input logic clk,
input logic reset,
input logic StallF, StallD, StallE, StallM,
input logic FlushD, FlushE, FlushM,

6
pipelined/src/ifu/bpred/gshare.sv
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@ -28,10 +28,8 @@
`include "wally-config.vh"
module gshare
#(parameter int k = 10
)
(input logic clk,
module gshare #(parameter k = 10) (
input logic clk,
input logic reset,
input logic StallF, StallD, StallE, StallM,
input logic FlushD, FlushE, FlushM,

9
pipelined/src/ifu/bpred/localHistoryPredictor.sv
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@ -28,11 +28,9 @@
`include "wally-config.vh"
module localHistoryPredictor
#( parameter int m = 6, // 2^m = number of local history branches
parameter int k = 10 // number of past branches stored
)
(input logic clk,
module localHistoryPredictor #(parameter m = 6, // 2^m = number of local history branches
k = 10) ( // number of past branches stored
input logic clk,
input logic reset,
input logic StallF, StallE,
input logic [`XLEN-1:0] LookUpPC,
@ -41,7 +39,6 @@ module localHistoryPredictor
input logic [`XLEN-1:0] UpdatePC,
input logic UpdateEN, PCSrcE,
input logic [1:0] UpdatePrediction
);
logic [2**m-1:0][k-1:0] LHRNextF;

6
pipelined/src/ifu/bpred/optgshare.sv
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@ -28,10 +28,8 @@
`include "wally-config.vh"
module optgshare
#(parameter int k = 10
)
(input logic clk,
module optgshare #(parameter k = 10) (
input logic clk,
input logic reset,
input logic StallF, StallD, StallE, StallM, StallW,
input logic FlushD, FlushE, FlushM, FlushW,

6
pipelined/src/ifu/bpred/speculativeglobalhistory.sv
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@ -28,10 +28,8 @@
`include "wally-config.vh"
module speculativeglobalhistory
#(parameter int k = 10
)
(input logic clk,
module speculativeglobalhistory #(parameter k = 10) (
input logic clk,
input logic reset,
input logic StallF, StallD, StallE, StallM, StallW,
input logic FlushD, FlushE, FlushM, FlushW,

6
pipelined/src/ifu/bpred/speculativegshare.sv
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@ -28,10 +28,8 @@
`include "wally-config.vh"
module speculativegshare
#(parameter int k = 10
)
(input logic clk,
module speculativegshare #(parameter k = 10) (
input logic clk,
input logic reset,
input logic StallF, StallD, StallE, StallM, StallW,
input logic FlushD, FlushE, FlushM, FlushW,

6
pipelined/src/ifu/bpred/twoBitPredictor.sv
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@ -28,10 +28,8 @@
`include "wally-config.vh"
module twoBitPredictor
#(parameter int k = 10
)
(input logic clk,
module twoBitPredictor #(parameter k = 10) (
input logic clk,
input logic reset,
input logic StallF, StallD, StallE, StallM,
input logic FlushD, FlushE, FlushM,