From 717cb4e6c50830f961e2d00ee34a1ac6d67c9843 Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 27 Jan 2023 14:27:04 -0800 Subject: [PATCH] Removed int/integer from parameters) --- pipelined/src/ebu/ahbcacheinterface.sv | 8 ++--- pipelined/src/ebu/buscachefsm.sv | 4 +-- pipelined/src/ifu/bpred/RAsPredictor.sv | 24 +++++++------- pipelined/src/ifu/bpred/btb.sv | 32 +++++++++---------- pipelined/src/ifu/bpred/foldedgshare.sv | 27 +++++++--------- pipelined/src/ifu/bpred/globalhistory.sv | 26 +++++++-------- pipelined/src/ifu/bpred/gshare.sv | 24 +++++++------- .../src/ifu/bpred/localHistoryPredictor.sv | 29 ++++++++--------- pipelined/src/ifu/bpred/optgshare.sv | 26 +++++++-------- .../src/ifu/bpred/speculativeglobalhistory.sv | 26 +++++++-------- pipelined/src/ifu/bpred/speculativegshare.sv | 28 ++++++++-------- pipelined/src/ifu/bpred/twoBitPredictor.sv | 24 +++++++------- 12 files changed, 128 insertions(+), 150 deletions(-) diff --git a/pipelined/src/ebu/ahbcacheinterface.sv b/pipelined/src/ebu/ahbcacheinterface.sv index a127e0fab..8bd1bc083 100644 --- a/pipelined/src/ebu/ahbcacheinterface.sv +++ b/pipelined/src/ebu/ahbcacheinterface.sv @@ -30,10 +30,10 @@ `include "wally-config.vh" module ahbcacheinterface #( - parameter integer BEATSPERLINE, // Number of AHBW words (beats) in cacheline - parameter integer AHBWLOGBWPL, // Log2 of ^ - parameter integer LINELEN, // Number of bits in cacheline - parameter integer LLENPOVERAHBW // Number of AHB beats in a LLEN word. AHBW cannot be larger than LLEN. (implementation limitation) + parameter BEATSPERLINE, // Number of AHBW words (beats) in cacheline + parameter AHBWLOGBWPL, // Log2 of ^ + parameter LINELEN, // Number of bits in cacheline + parameter LLENPOVERAHBW // Number of AHB beats in a LLEN word. AHBW cannot be larger than LLEN. (implementation limitation) )( input logic HCLK, HRESETn, // bus interface controls diff --git a/pipelined/src/ebu/buscachefsm.sv b/pipelined/src/ebu/buscachefsm.sv index c3be92fd8..8467f3029 100644 --- a/pipelined/src/ebu/buscachefsm.sv +++ b/pipelined/src/ebu/buscachefsm.sv @@ -32,8 +32,8 @@ // HCLK and clk must be the same clock! module buscachefsm #( - parameter integer BeatCountThreshold, // Largest beat index - parameter integer AHBWLOGBWPL // Log2 of BEATSPERLINE + parameter BeatCountThreshold, // Largest beat index + parameter AHBWLOGBWPL // Log2 of BEATSPERLINE )( input logic HCLK, input logic HRESETn, diff --git a/pipelined/src/ifu/bpred/RAsPredictor.sv b/pipelined/src/ifu/bpred/RAsPredictor.sv index c71ff2966..ae5b31999 100644 --- a/pipelined/src/ifu/bpred/RAsPredictor.sv +++ b/pipelined/src/ifu/bpred/RAsPredictor.sv @@ -28,19 +28,17 @@ `include "wally-config.vh" -module RASPredictor - #(parameter int StackSize = 16 - ) - (input logic clk, - input logic reset, - input logic PopF, - output logic [`XLEN-1:0] RASPCF, - input logic [3:0] WrongPredInstrClassD, - input logic [3:0] InstrClassD, - input logic PushE, - input logic incr, - input logic [`XLEN-1:0] PCLinkE - ); +module RASPredictor #(parameter StackSize = 16) ( + input logic clk, + input logic reset, + input logic PopF, + output logic [`XLEN-1:0] RASPCF, + input logic [3:0] WrongPredInstrClassD, + input logic [3:0] InstrClassD, + input logic PushE, + input logic incr, + input logic [`XLEN-1:0] PCLinkE +); // *** need to update so it either doesn't push until the memory stage // or need to repair flushed push. diff --git a/pipelined/src/ifu/bpred/btb.sv b/pipelined/src/ifu/bpred/btb.sv index 5f725b83a..c228964da 100644 --- a/pipelined/src/ifu/bpred/btb.sv +++ b/pipelined/src/ifu/bpred/btb.sv @@ -30,23 +30,21 @@ `include "wally-config.vh" -module btb - #(parameter int Depth = 10 - ) - (input logic clk, - input logic reset, - input logic StallF, StallE, - input logic [`XLEN-1:0] PCNextF, - output logic [`XLEN-1:0] BTBPredPCF, - output logic [3:0] InstrClass, - output logic Valid, - // update - input logic UpdateEN, - input logic [`XLEN-1:0] PCE, - input logic [`XLEN-1:0] IEUAdrE, - input logic [3:0] InstrClassE, - input logic UpdateInvalid - ); +module btb #(parameter Depth = 10) ( + input logic clk, + input logic reset, + input logic StallF, StallE, + input logic [`XLEN-1:0] PCNextF, + output logic [`XLEN-1:0] BTBPredPCF, + output logic [3:0] InstrClass, + output logic Valid, + // update + input logic UpdateEN, + input logic [`XLEN-1:0] PCE, + input logic [`XLEN-1:0] IEUAdrE, + input logic [3:0] InstrClassE, + input logic UpdateInvalid +); localparam TotalDepth = 2 ** Depth; logic [TotalDepth-1:0] ValidBits; diff --git a/pipelined/src/ifu/bpred/foldedgshare.sv b/pipelined/src/ifu/bpred/foldedgshare.sv index 2dfa48244..9de5d5c95 100644 --- a/pipelined/src/ifu/bpred/foldedgshare.sv +++ b/pipelined/src/ifu/bpred/foldedgshare.sv @@ -28,22 +28,19 @@ `include "wally-config.vh" -module foldedgshare - #(parameter int k = 16, - parameter int depth = 10 - ) - (input logic clk, - input logic reset, - input logic StallF, StallD, StallE, StallM, StallW, - input logic FlushD, FlushE, FlushM, FlushW, +module foldedgshare #(parameter k = 16, depth = 10) ( + input logic clk, + input logic reset, + input logic StallF, StallD, StallE, StallM, StallW, + input logic FlushD, FlushE, FlushM, FlushW, // input logic [`XLEN-1:0] LookUpPC, - output logic [1:0] DirPredictionF, - output logic DirPredictionWrongE, - // update - input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM, - input logic BranchInstrF, BranchInstrD, BranchInstrE, BranchInstrM, BranchInstrW, - input logic PCSrcE - ); + output logic [1:0] DirPredictionF, + output logic DirPredictionWrongE, + // update + input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM, + input logic BranchInstrF, BranchInstrD, BranchInstrE, BranchInstrM, BranchInstrW, + input logic PCSrcE +); logic MatchF, MatchD, MatchE, MatchM, MatchW; logic MatchNextX, MatchXF; diff --git a/pipelined/src/ifu/bpred/globalhistory.sv b/pipelined/src/ifu/bpred/globalhistory.sv index 7aa86dbb9..a8493a8d4 100644 --- a/pipelined/src/ifu/bpred/globalhistory.sv +++ b/pipelined/src/ifu/bpred/globalhistory.sv @@ -28,20 +28,18 @@ `include "wally-config.vh" -module globalhistory - #(parameter int k = 10 - ) - (input logic clk, - input logic reset, - input logic StallF, StallD, StallE, StallM, - input logic FlushD, FlushE, FlushM, -// input logic [`XLEN-1:0] LookUpPC, - output logic [1:0] DirPredictionF, - output logic DirPredictionWrongE, - // update - input logic [`XLEN-1:0] PCNextF, PCM, - input logic BranchInstrE, BranchInstrM, PCSrcE - ); +module globalhistory #(parameter k = 10) ( + input logic clk, + input logic reset, + input logic StallF, StallD, StallE, StallM, + input logic FlushD, FlushE, FlushM, + // input logic [`XLEN-1:0] LookUpPC, + output logic [1:0] DirPredictionF, + output logic DirPredictionWrongE, + // update + input logic [`XLEN-1:0] PCNextF, PCM, + input logic BranchInstrE, BranchInstrM, PCSrcE +); logic [1:0] DirPredictionD, DirPredictionE; logic [1:0] NewDirPredictionE, NewDirPredictionM; diff --git a/pipelined/src/ifu/bpred/gshare.sv b/pipelined/src/ifu/bpred/gshare.sv index ce189d268..2fb0c6eaf 100644 --- a/pipelined/src/ifu/bpred/gshare.sv +++ b/pipelined/src/ifu/bpred/gshare.sv @@ -28,20 +28,18 @@ `include "wally-config.vh" -module gshare - #(parameter int k = 10 - ) - (input logic clk, - input logic reset, - input logic StallF, StallD, StallE, StallM, - input logic FlushD, FlushE, FlushM, +module gshare #(parameter k = 10) ( + input logic clk, + input logic reset, + input logic StallF, StallD, StallE, StallM, + input logic FlushD, FlushE, FlushM, // input logic [`XLEN-1:0] LookUpPC, - output logic [1:0] DirPredictionF, - output logic DirPredictionWrongE, - // update - input logic [`XLEN-1:0] PCNextF, PCM, - input logic BranchInstrE, BranchInstrM, PCSrcE - ); + output logic [1:0] DirPredictionF, + output logic DirPredictionWrongE, + // update + input logic [`XLEN-1:0] PCNextF, PCM, + input logic BranchInstrE, BranchInstrM, PCSrcE +); logic [k-1:0] IndexNextF, IndexM; logic [1:0] DirPredictionD, DirPredictionE; diff --git a/pipelined/src/ifu/bpred/localHistoryPredictor.sv b/pipelined/src/ifu/bpred/localHistoryPredictor.sv index 1709772dd..cde1fa7d3 100644 --- a/pipelined/src/ifu/bpred/localHistoryPredictor.sv +++ b/pipelined/src/ifu/bpred/localHistoryPredictor.sv @@ -28,23 +28,20 @@ `include "wally-config.vh" -module localHistoryPredictor - #( parameter int m = 6, // 2^m = number of local history branches - parameter int k = 10 // number of past branches stored - ) - (input logic clk, - input logic reset, - input logic StallF, StallE, - input logic [`XLEN-1:0] LookUpPC, - output logic [1:0] Prediction, - // update - input logic [`XLEN-1:0] UpdatePC, - input logic UpdateEN, PCSrcE, - input logic [1:0] UpdatePrediction - - ); +module localHistoryPredictor #(parameter m = 6, // 2^m = number of local history branches + k = 10) ( // number of past branches stored + input logic clk, + input logic reset, + input logic StallF, StallE, + input logic [`XLEN-1:0] LookUpPC, + output logic [1:0] Prediction, + // update + input logic [`XLEN-1:0] UpdatePC, + input logic UpdateEN, PCSrcE, + input logic [1:0] UpdatePrediction +); - logic [2**m-1:0] [k-1:0] LHRNextF; + logic [2**m-1:0][k-1:0] LHRNextF; logic [k-1:0] LHRF, ForwardLHRNext, LHRFNext; logic [m-1:0] LookUpPCIndex, UpdatePCIndex; logic [1:0] PredictionMemory; diff --git a/pipelined/src/ifu/bpred/optgshare.sv b/pipelined/src/ifu/bpred/optgshare.sv index 1f99cfd26..78c98c5e6 100644 --- a/pipelined/src/ifu/bpred/optgshare.sv +++ b/pipelined/src/ifu/bpred/optgshare.sv @@ -28,21 +28,19 @@ `include "wally-config.vh" -module optgshare - #(parameter int k = 10 - ) - (input logic clk, - input logic reset, - input logic StallF, StallD, StallE, StallM, StallW, - input logic FlushD, FlushE, FlushM, FlushW, +module optgshare #(parameter k = 10) ( + input logic clk, + input logic reset, + input logic StallF, StallD, StallE, StallM, StallW, + input logic FlushD, FlushE, FlushM, FlushW, // input logic [`XLEN-1:0] LookUpPC, - output logic [1:0] DirPredictionF, - output logic DirPredictionWrongE, - // update - input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM, - input logic BranchInstrF, BranchInstrD, BranchInstrE, BranchInstrM, BranchInstrW, - input logic PCSrcE - ); + output logic [1:0] DirPredictionF, + output logic DirPredictionWrongE, + // update + input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM, + input logic BranchInstrF, BranchInstrD, BranchInstrE, BranchInstrM, BranchInstrW, + input logic PCSrcE +); logic MatchF, MatchD, MatchE, MatchM, MatchW; logic MatchNextX, MatchXF; diff --git a/pipelined/src/ifu/bpred/speculativeglobalhistory.sv b/pipelined/src/ifu/bpred/speculativeglobalhistory.sv index 094adca99..232351c86 100644 --- a/pipelined/src/ifu/bpred/speculativeglobalhistory.sv +++ b/pipelined/src/ifu/bpred/speculativeglobalhistory.sv @@ -28,21 +28,19 @@ `include "wally-config.vh" -module speculativeglobalhistory - #(parameter int k = 10 - ) - (input logic clk, - input logic reset, - input logic StallF, StallD, StallE, StallM, StallW, - input logic FlushD, FlushE, FlushM, FlushW, +module speculativeglobalhistory #(parameter k = 10) ( + input logic clk, + input logic reset, + input logic StallF, StallD, StallE, StallM, StallW, + input logic FlushD, FlushE, FlushM, FlushW, // input logic [`XLEN-1:0] LookUpPC, - output logic [1:0] DirPredictionF, - output logic DirPredictionWrongE, - // update - input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM, - input logic BranchInstrF, BranchInstrD, BranchInstrE, BranchInstrM, BranchInstrW, - input logic PCSrcE - ); + output logic [1:0] DirPredictionF, + output logic DirPredictionWrongE, + // update + input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM, + input logic BranchInstrF, BranchInstrD, BranchInstrE, BranchInstrM, BranchInstrW, + input logic PCSrcE +); logic MatchF, MatchD, MatchE, MatchM, MatchW; logic MatchNextX, MatchXF; diff --git a/pipelined/src/ifu/bpred/speculativegshare.sv b/pipelined/src/ifu/bpred/speculativegshare.sv index 05753c76d..98b590bed 100644 --- a/pipelined/src/ifu/bpred/speculativegshare.sv +++ b/pipelined/src/ifu/bpred/speculativegshare.sv @@ -28,22 +28,20 @@ `include "wally-config.vh" -module speculativegshare - #(parameter int k = 10 - ) - (input logic clk, - input logic reset, - input logic StallF, StallD, StallE, StallM, StallW, - input logic FlushD, FlushE, FlushM, FlushW, +module speculativegshare #(parameter k = 10) ( + input logic clk, + input logic reset, + input logic StallF, StallD, StallE, StallM, StallW, + input logic FlushD, FlushE, FlushM, FlushW, // input logic [`XLEN-1:0] LookUpPC, - output logic [1:0] DirPredictionF, - output logic DirPredictionWrongE, - // update - input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM, - input logic BranchInstrF, BranchInstrD, BranchInstrE, BranchInstrM, BranchInstrW, - input logic [3:0] WrongPredInstrClassD, - input logic PCSrcE - ); + output logic [1:0] DirPredictionF, + output logic DirPredictionWrongE, + // update + input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM, + input logic BranchInstrF, BranchInstrD, BranchInstrE, BranchInstrM, BranchInstrW, + input logic [3:0] WrongPredInstrClassD, + input logic PCSrcE +); logic MatchF, MatchD, MatchE, MatchM; logic MatchNextX, MatchXF; diff --git a/pipelined/src/ifu/bpred/twoBitPredictor.sv b/pipelined/src/ifu/bpred/twoBitPredictor.sv index 5a04a5fcf..4a7be674d 100644 --- a/pipelined/src/ifu/bpred/twoBitPredictor.sv +++ b/pipelined/src/ifu/bpred/twoBitPredictor.sv @@ -28,19 +28,17 @@ `include "wally-config.vh" -module twoBitPredictor - #(parameter int k = 10 - ) - (input logic clk, - input logic reset, - input logic StallF, StallD, StallE, StallM, - input logic FlushD, FlushE, FlushM, - input logic [`XLEN-1:0] PCNextF, PCM, - output logic [1:0] DirPredictionF, - output logic DirPredictionWrongE, - input logic BranchInstrE, BranchInstrM, - input logic PCSrcE - ); +module twoBitPredictor #(parameter k = 10) ( + input logic clk, + input logic reset, + input logic StallF, StallD, StallE, StallM, + input logic FlushD, FlushE, FlushM, + input logic [`XLEN-1:0] PCNextF, PCM, + output logic [1:0] DirPredictionF, + output logic DirPredictionWrongE, + input logic BranchInstrE, BranchInstrM, + input logic PCSrcE +); logic [k-1:0] IndexNextF, IndexM; logic [1:0] PredictionMemory;